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Ai Chip Design Rtl Jobs in Colorado (NOW HIRING)

Broadcom

Design Engineer

Fort Collins, CO

$60.20K - $96.30K/yr

Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

Broadcom, Inc.

Design Engineer

Fort Collins, CO · On-site

$60.20K - $96.30K/yr

Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

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Ai Chip Design Rtl information

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

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Design Engineer

Design Engineer

Broadcom

Fort Collins, CO

$60.20K - $96.30K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 10 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers

Job description

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Job Description:

Be part of the Custom Silicon Design Team within Broadcom's ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production.

Role Overview

This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands-on experience with the latest 3 nm and smaller process nodes. The role offers exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.

Key Responsibilities

  • Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).

  • Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).

  • Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff.

  • Utilize both commercial and in-house EDA tools for design, implementation, and verification.

  • Contribute to design flow improvements, automation, and deep sub-micron methodology development.

  • Assist in timing analysis, power planning, IR/EM checks, and post-route optimization.

  • Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.

  • Interface with customers and internal stakeholders to support technical discussions and design reviews.

Technical Skills / Background

  • Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.

  • Familiarity with ASIC physical design concepts such as placement, routing, and timing.

  • Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.

Coding and Tool Proficiency

  • Proficiency in UNIX/Linux environments.

  • Working knowledge of TCL; familiarity with Python or Perl preferred.

  • Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime is a plus.

Soft Skills

  • Excellent communication, collaboration, and problem-solving abilities.

  • Ability to work effectively with cross-functional and global teams.

  • Highly motivated, detail-oriented, and eager to learn in a fast-paced R&D environment.

  • Demonstrates strong engineering judgment, ownership, and accountability.

Education and Experience

  • Bachelor's degree in Electrical or Electronics Engineering, or

  • Master's degree in Electrical or Electronics Engineering.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$60,200 - $96,300.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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