Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ...
Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ...
Broadcom is seeking an IC package-design engineer for complex flip-chip-BGA packages for industry ... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ...
Broadcom is seeking an IC package-design engineer for complex flip-chip-BGA packages for industry ... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ...
Package Design Engineer
$141K - $226K/yr
Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ... AI), networking, high-performance computing (HPC), and 5G base stations. These designs include ...
Package Design Engineer
$141K - $226K/yr
Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages ... AI), networking, high-performance computing (HPC), and 5G base stations. These designs include ...
Senior Product Manager
$124K - $164K/yr
While deep protocol-level PCIe chip design expertise is not required, you must bring a strong, holistic understanding of modern data center server architectures-specifically AI/ML server topologies ...
Senior Product Manager
$124K - $164K/yr
While deep protocol-level PCIe chip design expertise is not required, you must bring a strong, holistic understanding of modern data center server architectures-specifically AI/ML server topologies ...
Come join the team creating technology that fuels the next generation AI/ML networks, mobile ... BSEE and 18+ years of industry experience in RTL design is a must, or MSEE and 16 experience using ...
Come join the team creating technology that fuels the next generation AI/ML networks, mobile ... BSEE and 18+ years of industry experience in RTL design is a must, or MSEE and 16 experience using ...
Design Engineer
Fort Collins, CO · On-site
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle -- from RTL to GDSII and silicon bring‑up.
Design Engineer
Fort Collins, CO · On-site
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle -- from RTL to GDSII and silicon bring‑up.
R&D Engineer IC Design
Broomfield, CO · On-site
Come join the team creating technology that fuels the next generation AI/ML networks, mobile ... BSEE and 18+ years of industry experience in RTL design is a must, or MSEE and 16 experience using ...
R&D Engineer IC Design
Broomfield, CO · On-site
Come join the team creating technology that fuels the next generation AI/ML networks, mobile ... BSEE and 18+ years of industry experience in RTL design is a must, or MSEE and 16 experience using ...
... AI), networking, high-performance computing (HPC), and 5G base stations. These designs include ... BSEE/MSEE or similar field and 12+ years of experience in flip-chip-BGA package design, including ...
... AI), networking, high-performance computing (HPC), and 5G base stations. These designs include ... BSEE/MSEE or similar field and 12+ years of experience in flip-chip-BGA package design, including ...
HPC Middleware Developer
Boulder, CO · On-site
Our team works closely with networking chip design teams in co-designing new hardware features and ... Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing ...
HPC Middleware Developer
Boulder, CO · On-site
Our team works closely with networking chip design teams in co-designing new hardware features and ... Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing ...
... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ... BSEE/MSEE or similar field and 12+ years of experience in flip-chip-BGA package design, including ...
... AI), networking, high-performance computing (HPC), and 5G base stations.These designs include ... BSEE/MSEE or similar field and 12+ years of experience in flip-chip-BGA package design, including ...
Our team works closely with networking chip design teams in co-designing new hardware features and ... Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing ...
Our team works closely with networking chip design teams in co-designing new hardware features and ... Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing ...
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Design Engineer
Fort Collins, CO · On-site
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Design Engineer
Fort Collins, CO · On-site
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
... with cross‑discipline/site RTL, DFT and Implementation design teams along with product ... AMD's Responsible AI Policy is available. This posting is for an existing vacancy. #J-18808-Ljbffr
... with cross‑discipline/site RTL, DFT and Implementation design teams along with product ... AMD's Responsible AI Policy is available. This posting is for an existing vacancy. #J-18808-Ljbffr
Lead Verification Design Engineer - Denver, CO - ZR_88_JOB
Denver, CO · On-site
$140K - $170K/yr
Our services include customer specific design assistance, design flow, RTL-to-GDSII implementation ... defense, AI, and high-performance computing. As a Lead Verification Engineer you will be ...
Lead Verification Design Engineer - Denver, CO - ZR_88_JOB
Denver, CO · On-site
$140K - $170K/yr
Our services include customer specific design assistance, design flow, RTL-to-GDSII implementation ... defense, AI, and high-performance computing. As a Lead Verification Engineer you will be ...
Post-Silicon Validation Engineer
Fort Collins, CO · On-site
$156K/yr
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.
Post-Silicon Validation Engineer
Fort Collins, CO · On-site
$156K/yr
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy. #J-18808 ...
... with cross-discipline/site RTL, DFT and Implementation design teams along with product ... AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy. #J-18808 ...
FPGA Designer
Denver, CO · On-site
$126K - $174K/yr
RTL design and verification including test benches, functional simulations, and timing closure ... Embraces AI as part of a modern engineering toolkit * Degree as a B.A.Sc., B.Eng. or equivalent
FPGA Designer
Denver, CO · On-site
$126K - $174K/yr
RTL design and verification including test benches, functional simulations, and timing closure ... Embraces AI as part of a modern engineering toolkit * Degree as a B.A.Sc., B.Eng. or equivalent
FPGA Engineer with Security Clearance
Broomfield, CO · On-site
$143K - $191K/yr
Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns ... This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ...
FPGA Engineer with Security Clearance
Broomfield, CO · On-site
$143K - $191K/yr
Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns ... This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL ...
Engineering - FPGA Design/Verification Engineer
Littleton, CO · On-site
$125K - $172K/yr
... chip (SoC) technologies. This role is ideal for experienced engineers seeking new technical ... AI prompting relevant to FPGA development - Demonstrated self-starter mindset and high Emotional ...
Engineering - FPGA Design/Verification Engineer
Littleton, CO · On-site
$125K - $172K/yr
... chip (SoC) technologies. This role is ideal for experienced engineers seeking new technical ... AI prompting relevant to FPGA development - Demonstrated self-starter mindset and high Emotional ...
Ai Chip Design Rtl information
What is an AI Chip Design RTL engineer?
What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?
What are common challenges faced by AI Chip Design RTL engineers during the verification process?
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
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Cities in Colorado with the most Ai Chip Design Rtl job openings:

Package Design Engineer
Fort Collins, CO
$134K/yr
Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 14 days ago
Broadcom rating
8.7
Based on 23 frontline employees who took The Breakroom Quiz
Job description
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Job Description:Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations.These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.
RESPONSIBILITIES:
Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
General flip-chip BGA package design & engineering
Project management and customer interface for your design projects
Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.
Physical design (layout) is a foundational responsibility in this role
EDUCATION/EXPERIENCE & REQUIREMENTS:
BSEE or similar field and 8+ years' experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years' work experience
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
Self-management and organization skills
Preferred candidates will also have1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
OTHER REQUIREMENTS
This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.
Compensation and Benefits
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
About Broadcom
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
10,000+ Employees
Headquarters location
Palo Alto, CA, US
Year founded
1991