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Cpu Design Verification Engineer Jobs in Colorado

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer ...

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer ...

Design Verification Engineer

Broomfield, CO · On-site

$108K - $172.80K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer ...

Develop and execute verification plans for IP blocks at both block and system levels * Build and ... Knowledge of CPU, DDR, bus, network protocols, or DSP design * Experience with AI-assisted ...

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Cpu Design Verification Engineer information

See Colorado salary details

$110.9K

$156.8K

$175.6K

How much do cpu design verification engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for cpu design verification engineer in Colorado is $156,833.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,000.00 and $174,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a CPU Design Verification Engineer, and why are they important?

To thrive as a CPU Design Verification Engineer, you need a strong background in computer architecture, digital logic design, and experience with hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with verification methodologies such as UVM/SystemVerilog, simulation tools, and debugging environments is essential. Analytical thinking, attention to detail, and strong teamwork and communication skills help engineers find and resolve complex design issues efficiently. These skills and qualities are crucial to ensure CPU designs are robust, functionally correct, and meet performance and quality targets before production.

What are some common challenges faced by CPU Design Verification Engineers during project cycles?

CPU Design Verification Engineers often encounter challenges such as managing complex testbench environments, ensuring thorough coverage of all functional scenarios, and debugging intricate issues that may arise during simulation. They must also coordinate closely with design and architecture teams to clarify specifications and quickly resolve ambiguities. Balancing tight project deadlines with the need for exhaustive verification is another frequent challenge, requiring strong organizational and problem-solving skills.

What does a CPU Design Verification Engineer do?

A CPU Design Verification Engineer is responsible for ensuring that the design of a CPU (Central Processing Unit) meets its specifications and functions correctly before it is manufactured. They create and run various tests and simulations to identify bugs or design issues, working closely with design and architecture teams to resolve problems. Their work helps ensure high-quality, reliable CPUs for use in computers, smartphones, and other electronic devices.

What is the difference between Cpu Design Verification Engineer vs Cpu Validation Engineer?

AspectCpu Design Verification EngineerCpu Validation Engineer
Primary FocusVerifying the correctness of CPU design through simulation and testing during developmentValidating the CPU's performance and functionality in real-world scenarios post-design
Work EnvironmentDesign teams, simulation labs, hardware description languagesTesting labs, hardware platforms, system integration environments
Required SkillsHardware description languages (Verilog/VHDL), simulation tools, debuggingHardware testing, scripting, performance analysis

While both roles focus on CPU quality, the Cpu Design Verification Engineer concentrates on verifying the design before manufacturing, whereas the Cpu Validation Engineer tests the CPU in real-world conditions after production. Both roles are essential in ensuring a reliable and high-performance CPU.

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What job categories do people searching Cpu Design Verification Engineer jobs in Colorado look for? The top searched job categories for Cpu Design Verification Engineer jobs in Colorado are:
What cities in Colorado are hiring for Cpu Design Verification Engineer jobs? Cities in Colorado with the most Cpu Design Verification Engineer job openings:
Infographic showing various Cpu Design Verification Engineer job openings in Colorado as of May 2026, with employment types broken down into 78% Full Time, 14% Part Time, and 8% Contract. Highlights an 73% Physical, 1% Hybrid, and 26% Remote job distribution, with an average salary of $156,833 per year, or $75.4 per hour.
Design Verification Engineer

Design Verification Engineer

Broadcom

Fort Collins, CO

$108K - $172.80K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 5 days ago


Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

12th of 137 rated electronics manufacturers


Job description

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Job Description:

Design Verification Engineer

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments.

Position Description:

The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.

The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements

  • 6+ years of experience with verification concepts and architectures for complex digital and MXS circuits

  • Experience verifying designs at the block and system levels.

  • Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)

  • Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits

  • Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)

  • Experience with Synopsys, Cadence, and Mentor simulations tools

  • Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments

  • Experience with Perl/Python and Tcl or other scripting languages

  • Experience with version control systems (DesignSync, git)

  • Superior writing, grammar, and verbal communication skills

  • Excellent problem solver; develops and employs automated processes where applicable

  • Worked independently and in a global team and dynamic environment in a highly visible role

  • Possesses ability to learn and adapt to new tools and methodologies on the fly

  • Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:

  • Experience with hardware design and debug

  • Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms

  • Formal verification concepts / experience is a plus

  • Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus

  • Experience with co-simulation a plus

Education and Experience required:

  • BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is$108,000 - $172,800.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.


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