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Uvm Foundation Jobs (NOW HIRING)

Axiado

ASIC Verification Engineer

San Jose, CA · On-site

... systems at the foundation levels of hardware, independent of host CPUs and operating systems ... Qualifications * 8+ years of experience in UVM verification and UVM environment development (must ...

Apple

Graphics Design Verification Engineer

Austin, TX

$134K - $164K/yr

A strong computer architecture background, preferably in graphics, and a solid foundation in ... Port legacy test bench components in System Verilog and Universal Verification Methodology (UVM ...

Apple

Graphics Design Verification Engineer

Austin, TX

$134K - $164K/yr

A strong computer architecture background, preferably in graphics, and a solid foundation in ... Architect test bench methodology using Universal Verification Methodology (UVM) and System Verilog ...

Apple

Graphics Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

A strong computer architecture background, preferably in graphics, and a solid foundation in ... Port legacy test bench components in System Verilog and Universal Verification Methodology (UVM ...

Axiado

ASIC Verification Engineer

San Jose, CA · On-site

... systems at the foundation levels of hardware, independent of host CPUs and operating systems ... Qualifications * 8+ years of experience in UVM verification and UVM environment development (must ...

Apple

Graphics Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

A strong computer architecture background, preferably in graphics, and a solid foundation in ... Architect test bench methodology using Universal Verification Methodology (UVM) and System Verilog ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

... silicon foundation for our software platform from the ground up. We're building a tight-knit ... Fluent in System verilog/System-C and UVM. * Experience verifying designs with multiple power ...

Anodize

Lead SoC Verification Engineer

Los Altos, CA · On-site

$161K/yr

... silicon foundation for our software platform from the ground up. We're building a tight-knit ... Fluent in System verilog/System-C and UVM. * Experience verifying designs with multiple power ...

femtoAI

Hardware Engineer

San Bruno, CA · On-site

$147K - $194K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

Strong foundation in digital design, computer architecture, and VLSI through coursework or projects ... Proficiency with UVM design verification frameworks * Knowledge of physical design and verification

Apple

GPU Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

A strong computer architecture background, and a solid foundation in verification methodology is ... Experience with common verification methodologies such as UVM. Experience defining coverage space ...

Micron Technology

Sr. Design Verification Engineer

Minneapolis, MN · On-site

$142K - $173K/yr

  • Medical

  • Dental

  • Vision

  • PTO

We build the verification foundation that ensures Micron's most advanced ASICs work exactly as ... Develop and maintain UVM-based SystemVerilog verification environments * Define and execute block ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ... Our world-class team is the foundation of our company, and our innovative spirit drives us to ...

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Uvm Foundation information

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How much do uvm foundation jobs pay per hour?

As of Aug 17, 2026, the average hourly pay for uvm foundation in the United States is $39.30, according to ZipRecruiter salary data. Most workers in this role earn between $30.29 and $45.67 per hour, depending on experience, location, and employer.

What is the UVM Foundation?

The UVM Foundation is a nonprofit organization dedicated to supporting the University of Vermont through fundraising and alumni engagement. It works to secure private donations that fund scholarships, faculty positions, research, and campus initiatives. The Foundation partners with alumni, parents, and friends to strengthen the university's financial resources and support its strategic goals. By fostering a culture of philanthropy, the UVM Foundation helps ensure long-term success for the university and its students.

What are some typical challenges faced by professionals working at a university foundation like the UVM Foundation?

Professionals at a university foundation such as the UVM Foundation often navigate the challenge of balancing donor expectations with the institution’s priorities. They work in a dynamic environment where building and maintaining long-term donor relationships is key, requiring strong communication and interpersonal skills. Additionally, they frequently collaborate with academic leaders, alumni, and external partners to align fundraising initiatives with strategic goals, which can involve managing multiple projects and deadlines simultaneously. Team members are also expected to stay current on fundraising best practices and comply with ethical standards in philanthropy.

What are the key skills and qualifications needed to thrive at the UVM Foundation, and why are they important?

To thrive at the UVM Foundation, you need strong fundraising expertise, donor relations experience, and a background in nonprofit management or development, often supported by a relevant degree. Familiarity with donor management systems like Raiser's Edge and proficiency in Microsoft Office Suite are commonly required. Outstanding communication, networking, and organizational skills help build lasting relationships and manage multiple projects. These capabilities are crucial for securing philanthropic support, maintaining donor satisfaction, and advancing the foundation’s mission.

What is the difference between Uvm Foundation vs Uvm Technician?

AspectUvm FoundationUvm Technician
CertificationsTypically requires basic safety and construction certificationsRequires similar certifications, often with additional technical training
Work EnvironmentPrimarily on construction sites, focusing on foundational workOn-site, performing technical tasks related to Uvm systems
Employer & Industry UsageUsed in construction, civil engineering, infrastructure projectsCommon in maintenance, installation, and repair of Uvm systems

The Uvm Foundation role focuses on laying the groundwork for Uvm systems, involving foundational construction tasks. In contrast, the Uvm Technician handles technical installation, maintenance, and repair of Uvm systems. Both roles require relevant certifications and work in similar environments, but they differ in technical complexity and responsibilities.

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The top searched job categories for Uvm Foundation jobs are:

Uvm Foundation jobs near you
Infographic showing various Uvm Foundation job openings in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $81,752 per year, or $39.3 per hour.

Senior Staff Design Verification Engineer

Cirrus Logic

Chandler, AZ • On-site

$133K - $163K/yr

Full-time

Re-posted 5 days ago

Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high-quality mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level designs, contributing to advanced verification methodologies and infrastructure.
This position offers exposure to multiple verification domains including UVM-based testbench development, formal verification, hardware emulation/acceleration, gate-level simulations, and software-driven verification in a highly collaborative and technically rigorous environment.
Responsibilities:
  • Develop comprehensive verification plans aligned with design and system requirements.
  • Perform functional verification of custom mixed-signal ASICs at block and chip level.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage.
  • Implement, analyze, and drive functional and code coverage, including coverage closure.
  • Conduct failure analysis, regression triage, and debug, resolving functional and timing-related issues.
  • Run and debug gate-level simulations, including timing violations and back-annotation issues.
  • Develop and maintain digital and mixed-signal behavioral models to support verification.
  • Support verification flow and infrastructure development, including regressions and automation.
  • Collaborate cross-functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.
  • Contribute to both pre-silicon verification and post-silicon validation efforts.
  • Proactively improve verification methodologies, processes, and best practices.

Required Knowledge, Skills, and Experience:
  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
    • Bachelor's with 10+ years of relevant experience.
    • Master's with 8+ years of relevant experience.
    • PhD with 6+ years of relevant experience.
  • Significant industry experience in silicon design and/or ASIC verification.
  • Strong proficiency with HDLs: Verilog and/or VHDL.
  • Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
  • Solid understanding of digital design principles and system architecture.
  • Hands-on experience with:
    • Testbench architecture and stimulus generation.
    • Regression execution and debug.
    • Coverage analysis and closure.
  • Ability to work effectively in a cross-disciplinary, team-oriented environment.

Preferred Knowledge, Skills, and Experience:
  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA).
  • Exposure to or hands-on experience with:
    • Formal verification
    • Hardware emulation or acceleration
    • Software-driven verification
  • Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.

#LI-Hybrid
#LI-EK1
#HOTT
Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

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