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Sta Static Timing Analysis Engineer Jobs (NOW HIRING)

Etched

ASIC Timing Engineer

Cupertino, CA

$2.0K/mo

ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative ... Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC ...

Etched

ASIC Timing Engineer

Cupertino, CA · On-site

$2.0K/mo

ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative ... Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC ...

Etched

ASIC Timing Engineer

Cupertino, CA

$2.0K/mo

ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative ... Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC ...

Efficient Computer

Lead STA Engineer

San Jose, CA · On-site

$200K - $250K/yr

... STA Engineer to join our growing team. The Timing Lead will work on timing convergence and ... Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage ...

Apple

CPU CDC/STA Engineer

Santa Clara, CA

$150K - $277K/yr

As a CPU CDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions ...

Apple

CPU CDC/STA Engineer

Santa Clara, CA

$129K - $194K/yr

As a CPU CDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions ...

Apple

CPU Design Timing Engineer

Santa Clara, CA · On-site

Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... static timing analysis, noise analysis, and fixing noise in designs Experience with variation ...

Apple

CPU Design Timing Engineer

Santa Clara, CA · On-site

Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... static timing analysis, noise analysis, and fixing noise in designs Experience with variation ...

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Sta Static Timing Analysis Engineer information

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How much do sta static timing analysis engineer jobs pay per hour?

As of Jul 15, 2026, the average hourly pay for sta static timing analysis engineer in the United States is $53.63, according to ZipRecruiter salary data. Most workers in this role earn between $43.27 and $62.26 per hour, depending on experience, location, and employer.

What are STA (Static Timing Analysis) Engineers?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA Static Timing Analysis Engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a Static Timing Analysis (STA) Engineer, and why are they important?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
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Infographic showing various Sta Static Timing Analysis Engineer job openings in the United States as of July 2026, with employment types broken down into 87% Full Time, 11% Part Time, and 2% Contract. Highlights an 83% Physical, 3% Hybrid, and 14% Remote job distribution, with an average salary of $111,552 per year, or $53.6 per hour.

ASIC Timing Engineer

Etched

Cupertino, CA

$2.0K/mo

Full-time

Medical, Dental, Vision

Posted 20 days ago

Job description

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

ASIC Timing Engineer

Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next-generation AI chips, ensuring that we meet the high-performance demands of our unique architecture.

Representative Projects:

  • Drive timing analysis and closure of chips at block, cluster, and full chip level
  • Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, and ensure timing and power convergence, as well as ECO implementation
  • Enhance timing convergence flows in partnership with our methodology teams
  • Contribute to DFT logic understanding and assist with DFT timing closure for various modes, such as scan and BIST
  • Work on timing closure of digital logic/macros in AMS designs/IPs, ensuring all aspects are addressed

You maybe a good fit if you have:

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 2+ years of experience in Timing and STA
  • Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC checks, and timing convergence, including timing constraints generation and management
  • Expertise in analyzing and fixing timing paths through ECOs, with a focus on crosstalk and noise analysis
  • In-depth knowledge of RTL to Netlist, industry-standard STA and timing convergence tools
  • Familiarity with deep sub-micron process nodes, including modeling and converging timing in these nodes
  • Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs, DPUs/Network processors, or SoCs
  • Experience in methodology and/or flow development, as well as automation

We encourage you to apply even if you do not believe you meet every single qualification.

How we're different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits:

  • Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino

Apply