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Sta Static Timing Analysis Engineer Jobs in Norridge, IL

Senior FPGA Engineer (Algo)

Chicago, IL · On-site

$150K - $250K/yr

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict ... Engineering, Computer Engineering, or a related field * Hands-on experience with RTL design in ...

FPGA Engineer

Chicago, IL · On-site

$133K - $172K/yr

Analyzing the results on a day to day basis and looking for methods to speed up designs Skills and ... Working on timing closure of designs/experience with STA * Experience with developing and verifying ...

FPGA Engineer

Chicago, IL · On-site

$133K - $172K/yr

FPGA Engineer, Chicago, IL FPGA Engineer candidates located outside of the Chicago area can work ... timing analysis and floor planning, and validating and analyzing designs for errors and efficiency.

FPGA Engineer

Chicago, IL · On-site

$133K - $172K/yr

Development experience with FPGAs (Verilog/VHDL, functional verification, and static timing closure ... reviewing applications, analyzing resumes, or assessing responses and identifying potential ...

FPGA Engineer

Chicago, IL · On-site

$133K - $172K/yr

FPGA Engineer, Chicago, IL A rapidly growing proprietary trading firm with offices in Chicago ... timing analysis and floor planning, and validating and analyzing designs for errors and efficiency.

FPGA Engineer

Chicago, IL · On-site

$175K - $225K/yr

Development experience with FPGAs (Verilog/VHDL, functional verification, and static timing closure ... reviewing applications, analyzing resumes, or assessing responses and identifying potential ...

FPGA Engineer

Chicago, IL

$175K - $225K/yr

Development experience with FPGAs (Verilog/VHDL, functional verification, and static timing closure ... reviewing applications, analyzing resumes, or assessing responses and identifying potential ...

FPGA Electrical Engineer, Chicago, IL We are seeking a talented and self-motivated FPGA Electrical ... timing analysis and floor planning, and validating and analyzing designs for errors and efficiency ...

FPGA Electrical Engineer, Chicago, IL Any FPGA Electrical Engineer located outside of the Chicago ... timing analysis and floor planning, and validating and analyzing designs for errors and efficiency.

FPGA Engineer - Work From Home

Chicago, IL · On-site +1

$133K - $172K/yr

FPGA Engineer - Work From Home We are seeking a talented and self-motivated FPGA Engineer to join a ... timing analysis and floor planning, and validating and analyzing designs for errors and efficiency ...

FPGA Engineer

Chicago, IL · On-site

$125K - $200K/yr

Analyzing the results on a day to day basis and looking for methods to speed up designs Skills and ... Working on timing closure of designs/experience with STA * Experience with developing and verifying ...

FPGA Firmware Developer

Batavia, IL · On-site

$99K - $130K/yr

Fermilab is seeking a FPGA Firmware Developer who will design, develop, verify, and integrate FPGA ... Performing simulation, verification, timing analysis, constraints development, and optimization.

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Sta Static Timing Analysis Engineer information

See Norridge, IL salary details

$25

$53

$76

How much do sta static timing analysis engineer jobs pay per hour?

As of Aug 30, 2026, the average hourly pay for sta static timing analysis engineer in Norridge, IL is $53.45, according to ZipRecruiter salary data. Most workers in this role earn between $43.12 and $62.07 per hour, depending on experience, location, and employer.

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What cities near Norridge, IL are hiring for Sta Static Timing Analysis Engineer jobs?

Cities near Norridge, IL with the most Sta Static Timing Analysis Engineer job openings:

Infographic showing various Sta Static Timing Analysis Engineer job openings in Norridge, IL as of August 2026, with employment types broken down into 86% Full Time, and 14% Part Time. Highlights an 100% In-person job distribution, with an average salary of $111,183 per year, or $53.5 per hour.

Senior FPGA Engineer (Algo)

Chicago, IL • On-site

$150K - $250K/yr

Full-time

Medical, Dental, Vision, Life, Retirement

Re-posted 22 days ago


Job description

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.
Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.
We operate with respect, curiosity and open minds. The people who thrive here share our belief that it's not just what we do that matters-it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.
We are currently seeking a FPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We're seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.
This role is for the Chicago office only.
Responsibilities:
  • Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
  • Research and evaluate a variety of cutting-edge FPGA hardware and technologies
  • Propose creative solutions to overcome FPGA/hardware limitations
  • Liaise directly with software and other design teams
  • Conduct lab debugging and characterization of new hardware

Candidate Requirements:
  • Bachelor's degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master's degree or higher also counts for experience)
  • Solid Hardware Engineering experience, especially with FPGA
  • Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
  • Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
  • Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
  • Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
  • Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
  • Knowledge of the TCP/IP stack
  • Strong working knowledge of either XILINX or ALTERA FPGA design flow
  • Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
  • Excellent research and data gathering skills

The annual base salary range for this position is $150,000 to $250,000 depending on the candidate's experience, qualifications, and relevant skill set. The position is also eligible for an annual discretionary bonus. In addition, DRW offers a comprehensive suite of employee benefits including group medical, pharmacy, dental and vision insurance, 401k (with discretionary employer match), short and long-term disability, life and AD&D insurance, health savings accounts, and flexible spending accounts.
For more information about DRW's processing activities and our use of job applicants' data, please view our Privacy Notice at https://drw.com/privacy-notice.
California residents, please review the California Privacy Notice for information about certain legal rights at https://drw.com/california-privacy-notice.
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