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Sta Static Timing Analysis Engineer Jobs in New York

P2P

Senior FPGA Engineer

Manhattan, NY · On-site

$225 - $325/hr

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

DRW

Senior FPGA Engineer

New York, NY · On-site

$225K - $325K/yr

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

We are looking for a hardware engineer to join our high frequency trading technology team ... Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis)

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

... timing analysis). • Knowledge of TCP/IP stack and on-chip networking applications. • Experience with C++ and Python. • Experience with functional verification and system level debugging. • ...

City of New York

Timing Engineer

Queens, NY · On-site

$90K - $100K/yr

... Timing & Intersection Control Unit ... The Assistant Civil Engineer performs engineering work related to the planning, design, analysis ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

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Sta Static Timing Analysis Engineer jobs near you
Infographic showing various Sta Static Timing Analysis Engineer job openings in New York as of August 2026, with employment types broken down into 83% Full Time, 14% Part Time, and 3% Contract. Highlights an 84% Physical, 4% Hybrid, and 12% Remote job distribution.

Hardware Engineer, Physical Design

Normal Computing

New York, NY • On-site

$200K - $400K/yr

Full-time

Posted 20 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow-optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.
What You Will Own
  • Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
  • Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
  • Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.
  • Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.
  • Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.
  • Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.

What Makes You a Great Fit
  • Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.
  • PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.
  • Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
  • Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.

Bonus Points
  • Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.
  • Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).
  • Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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