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Sta Static Timing Analysis Engineer Jobs in New York

P2P

Senior FPGA Engineer

Manhattan, NY · On-site

$225 - $325/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

DRW

Senior FPGA Engineer

New York, NY · On-site

$225K - $325K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

Architect and implement new FPGA applications (synthesis, place & route, static timing analysis ... Solid Hardware Engineering experience, especially with FPGA * Highly autonomous with a can-do ...

Cloud Peritus

Hardware Engineer

New York, NY

$135K - $178K/yr

We are looking for a hardware engineer to join our high frequency trading technology team ... Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis)

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

... timing analysis). • Knowledge of TCP/IP stack and on-chip networking applications. • Experience with C++ and Python. • Experience with functional verification and system level debugging. • ...

City of New York

Timing Engineer

Queens, NY · On-site

$90K - $100K/yr

... Timing & Intersection Control Unit ... The Assistant Civil Engineer performs engineering work related to the planning, design, analysis ...

Brooksource

Senior FPGA Engineer

Manhattan, NY · On-site

$80 - $90/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Senior FPGA Engineer Niskayuna, NY Hybrid role, 2-3 days / week onsite (Open to 1 week on / 1 week ... Deep understanding of synchronous digital design, clocked systems, state machines, timing analysis ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

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Sta Static Timing Analysis Engineer jobs near you
Infographic showing various Sta Static Timing Analysis Engineer job openings in New York as of August 2026, with employment types broken down into 1% Internship, 80% Full Time, 15% Part Time, 1% Temporary, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution.

Senior FPGA Engineer

P2P

Manhattan, NY • On-site

$225 - $325/hr

Other

Medical, Dental, Vision, Life, Retirement

Posted 8 days ago

Job description

DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk.

Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets.

We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it. DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.

We are currently seeking a Senior FPGA Engineer to join one of our trading teams in Chicago, NYC, or London. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build FPGA applications for existing teams. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.

Responsibilities
  • Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
  • Research and evaluate a variety of cutting-edge FPGA hardware and technologies
  • Propose creative solutions to overcome FPGA/hardware limitations
  • Liaise directly with software and other design teams
  • Conduct lab debugging and characterization of new hardware
Candidate Requirements
  • Bachelor’s degree or higher, Computer/Electrical Engineering with 3+ years of experience within the field; (Master’s degree or higher also counts for experience)
  • Solid Hardware Engineering experience, especially with FPGA
  • Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
  • Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
  • Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing Verilog
  • Experience in FPGA design flow including synthesis, place & route , static timing analysis is required
  • Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems, networking, and peripheral interconnect is required
  • Knowledge of the TCP/IP stack
  • Strong working knowledge of either XILINX or ALTERA FPGA design flow
  • Experience with functional verification utilizing high-level methodologies (e.g. System Verilog) is a plus.
  • Excellent research and data gathering skills

The annual base salary range for this position is $225,000 to $325,000 depending on the candidate’s experience, qualifications, and relevant skill set. The position is also eligible for an annual discretionary bonus. In addition, DRW offers a comprehensive suite of employee benefits including group medical, pharmacy, dental and vision insurance, 401k (with discretionary employer match), short and long-term disability, life and AD&D insurance, health savings accounts, and flexible spending accounts.

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