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Sta Static Timing Analysis Engineer Jobs in Missouri

Jobtailor

Physical Design Engineer

California, MO · On-site

$110 - $190/hr

Requirements * Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a ... In static timing analysis, floor planning, and power integrity analysis. * Strong knowledge of low ...

Jobtailor

Hardware Engineer, EDA Tools

California, MO · On-site

$120 - $180/hr

Join Intel's world-class team as an EDA Tools Hardware Engineer * Play a pivotal role in shaping ... Static timing analysis (STA) * Power grid design and IR drop concepts * Experience with large SoC ...

Garver

Traffic Analysis Engineer

Saint Louis, MO · On-site

$84K - $115K/yr

Garver is seeking a highly-motivated Traffic Analysis Engineer in our St. Louis, MO office to add ... Developing traffic signal timing plans * Preparing summary documentation and reports * Coordinating ...

Boeing

Lead Design and Analysis Engineer

Berkeley, MO

$96K - $126K/yr

  • Medical

  • Life

  • Retirement

Lead Design and Analysis Engineer Company: The Boeing Company Boeing Defense, Space & Security is ... timing budgets, synchronization, operational constraints, and integration assumptions. * Lead ...

Boeing

Lead Design and Analysis Engineer

Berkeley, MO · On-site

$96K - $126K/yr

  • Medical

  • Life

  • Retirement

Lead Design and Analysis Engineer Company: The Boeing Company Boeing Defense, Space & Security is ... timing budgets, synchronization, operational constraints, and integration assumptions. * Lead ...

Jobtailor

Senior ASIC Design Engineer

California, MO · On-site

$168 - $310.50/hr

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking Senior ASIC Design ... and timing analysis. * Exposure to Digital systems and VLSI design, Computer Architecture, and ...

Focus Financial Partners

BI & Data Engineer

Saint Louis, MO · On-site

$108K - $130K/yr

... static dashboards. * AI-Assisted Development: Leverage AI-assisted coding tools (e.g., GitHub ... Partner with data engineers and analytics engineers who build and maintain Snowflake semantic ...

Focus Financial Partners

BI & Data Engineer

Saint Louis, MO · Hybrid

$111K - $133K/yr

... static dashboards. * AI-Assisted Development: Leverage AI-assisted coding tools (e.g., GitHub ... Partner with data engineers and analytics engineers who build and maintain Snowflake semantic ...

Focus Financial Partners

BI & Data Engineer

Saint Louis, MO · On-site

$111K - $133K/yr

... static dashboards. * AI-Assisted Development: Leverage AI-assisted coding tools (e.g., GitHub ... Partner with data engineers and analytics engineers who build and maintain Snowflake semantic ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

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Physical Design Engineer

Jobtailor

California, MO • On-site

$110 - $190/hr

Other

This job post has expired today. Applications are no longer accepted.

Job description

Responsibilities
  • Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
  • Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
  • Conduct verification and signoff activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
  • Analyze results to identify and resolve violations related to timing, reliability, and design structure.
  • Optimize designs for power, performance, and area using industry-standard EDA tools.
  • Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
  • Collaborate with teams to address design challenges and deliver robust solutions.
Requirements
  • Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, and 3+ years of experience in physical design; OR a Master's degree in Electrical Engineering, Computer Engineering, or a related field, and 2+ years of experience in physical design; OR a PhD in Electrical Engineering, Computer Engineering, or a related field.
  • In RTL-to-GDS implementation, including synthesis, place and route, and timing closure.
  • In industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics for physical design tasks.
  • In static timing analysis, floor planning, and power integrity analysis.
  • Strong knowledge of low-power design techniques and methodologies.
Hard Skills
  • physical design implementation
  • RTL to GDS
  • synthesis
  • floor planning
  • place and route
  • clock tree synthesis
  • static timing analysis
  • power integrity analysis
  • design optimization
  • low-power design techniques
Soft Skills
  • collaboration
  • problem-solving
  • team efficiency
  • accuracy
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