We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
Beaverton, OR · On-site
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
Physical Design Engineer for Core IP
Hillsboro, OR · On-site
$148K - $152K/yr
Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of ...
Physical Design Engineer for Core IP
Hillsboro, OR · On-site
$148K - $152K/yr
Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of ...
Physical Design Engineer for Core IP
$148K - $152K/yr
Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of ...
Physical Design Engineer for Core IP
$148K - $152K/yr
Conducts verification and signoff including formal equivalence verification, static timing analysis ... Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU Design Timing Engineer
$181K - $318K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... with a static timing analysis tool such as PrimeTime ® or Tempus ® Experience with timing ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
CPU CDC/RDC/STA Engineer
$181K - $318K/yr
... and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. Description In this role, you will be: • Responsible for developing, improving, and ...
Senior Physical Design Engineer for Core IP
Hillsboro, OR · On-site
$164K - $269K/yr
Static Timing Analysis, Noise analysis, and reliability verification techniques * RTL to GDS ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior Physical Design Engineer for Core IP
Hillsboro, OR · On-site
$164K - $269K/yr
Static Timing Analysis, Noise analysis, and reliability verification techniques * RTL to GDS ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior Physical Design Engineer for Core IP
$164K - $269K/yr
Static Timing Analysis, Noise analysis, and reliability verification techniques * RTL to GDS ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior Physical Design Engineer for Core IP
$164K - $269K/yr
Static Timing Analysis, Noise analysis, and reliability verification techniques * RTL to GDS ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Senior CPU Core Physical Design Engineer
Hillsboro, OR · On-site
$148K - $152K/yr
The CPU Physical Design Engineer: * Performs physical design implementation of custom CPU designs ... Conducts verification and signoff including formal equivalence verification, static timing analysis ...
Senior CPU Core Physical Design Engineer
Hillsboro, OR · On-site
$148K - $152K/yr
The CPU Physical Design Engineer: * Performs physical design implementation of custom CPU designs ... Conducts verification and signoff including formal equivalence verification, static timing analysis ...
Senior CPU Core Physical Design Engineer
$148K - $152K/yr
The CPU Physical Design Engineer: * Performs physical design implementation of custom CPU designs ... Conducts verification and signoff including formal equivalence verification, static timing analysis ...
Senior CPU Core Physical Design Engineer
$148K - $152K/yr
The CPU Physical Design Engineer: * Performs physical design implementation of custom CPU designs ... Conducts verification and signoff including formal equivalence verification, static timing analysis ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... analysis flows, and physical design verification (LEC, DVS, etc.) Knowledge of static timing tools ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... analysis flows, and physical design verification (LEC, DVS, etc.) Knowledge of static timing tools ...
Sta Static Timing Analysis Engineer information
What are STA (Static Timing Analysis) Engineers?
STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.
What are some common challenges faced by STA Static Timing Analysis Engineers during project cycles?
STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.
What are the key skills and qualifications needed to thrive as a Static Timing Analysis (STA) Engineer, and why are they important?
To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
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Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.
What you'll be doing:
Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.
What we need to see:
BS (or equivalent experience) in Electrical or Computer Engineering with 5 years' experience or MS (or equivalent experience) with 3 years' experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Ways to stand out from the crowd:
Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs
Background in logic synthesis and equivalence checking/FV.
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
Understanding and timing closure of digital logic/macros in AMS designs/IPs.
Experience in methodology and/or flow development as well as automation.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993