Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Preferred Qualifications This position requires detailed knowledge of the ASIC ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Preferred Qualifications This position requires detailed knowledge of the ASIC ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
... synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
... synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
... and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical ... At least 8 years of experience in Physical Design and STA review.. * At least 8 years of experience ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
... and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical ... At least 8 years of experience in Physical Design and STA review.. * At least 8 years of experience ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$120 - $160/hr
SoC Physical Design Engineer, STA/Timing Description * Work with design teams to understand and ... Deep analysis of timing paths to identify key issues. * Implement timing infrastructure. Minimum ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$120 - $160/hr
SoC Physical Design Engineer, STA/Timing Description * Work with design teams to understand and ... Deep analysis of timing paths to identify key issues. * Implement timing infrastructure. Minimum ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... STA and/or Timing Closure. Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... STA and/or Timing Closure. Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
The Role and Impact As a Physical Design Timing Engineer, you will play a critical role in ... static timing analysis, timing constraint generation, and timing optimization techniques ...
The Role and Impact As a Physical Design Timing Engineer, you will play a critical role in ... static timing analysis, timing constraint generation, and timing optimization techniques ...
Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$170.40 - $272.60/hr
Provide technical guidance to junior engineers. * Turn abstract concepts and customer requirements ... Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ...
Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$170.40 - $272.60/hr
Provide technical guidance to junior engineers. * Turn abstract concepts and customer requirements ... Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ...
Senior FPGA Design Engineer (MTD, Tualatin, OR)
Tualatin, OR · On-site
$154.90 - $247.80/hr
Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ... Job Segment Design Engineer, Instrumentation, Electrical Engineering, Manufacturing Engineer, HVAC, ...
Senior FPGA Design Engineer (MTD, Tualatin, OR)
Tualatin, OR · On-site
$154.90 - $247.80/hr
Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ... Job Segment Design Engineer, Instrumentation, Electrical Engineering, Manufacturing Engineer, HVAC, ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
... Static Timing Analysis (STA). - Experience in validation development, pre-silicon testing, and DFT ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
... Static Timing Analysis (STA). - Experience in validation development, pre-silicon testing, and DFT ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... programming skills with TCL Preferred Qualifications Experience with large design STA and/or Timing ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... programming skills with TCL Preferred Qualifications Experience with large design STA and/or Timing ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... domain crossing checkers) Synthesis, static timing analysis, and design-for-test (DFT ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... domain crossing checkers) Synthesis, static timing analysis, and design-for-test (DFT ...
RTL Design Engineer
Beaverton, OR · On-site
... static timing analysis, and design-for-test (DFT) SystemVerilog assertions, checkers, and advanced verification techniques Scripting languages (Perl, Python) Formal verification and low-power design ...
RTL Design Engineer
Beaverton, OR · On-site
... static timing analysis, and design-for-test (DFT) SystemVerilog assertions, checkers, and advanced verification techniques Scripting languages (Perl, Python) Formal verification and low-power design ...
Physical Design Engineer
$141K - $145K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...
Physical Design Engineer
$141K - $145K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... programming skills with TCL
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... programming skills with TCL
Sta Static Timing Analysis Engineer information
What is a STA static timing analysis engineer?
STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.
What are some common challenges faced by STA static timing analysis engineers during project cycles?
STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.
What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?
To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Oregon?
For Sta Static Timing Analysis Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Sta Static Timing Analysis Engineer jobs in Oregon look for?
The top searched job categories for Sta Static Timing Analysis Engineer jobs in Oregon are:
What cities in Oregon are hiring for Sta Static Timing Analysis Engineer jobs?
Cities in Oregon with the most Sta Static Timing Analysis Engineer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976