CPU Design Timing Engineer
Beaverton, OR · On-site
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... analysis flows, and physical design verification (LEC, DVS, etc.) Knowledge of static timing tools ...
CPU Design Timing Engineer
Beaverton, OR · On-site
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level ... analysis flows, and physical design verification (LEC, DVS, etc.) Knowledge of static timing tools ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... analysis. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering.
Physical Design Engineer
Hillsboro, OR · On-site
$148K - $152K/yr
Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... Additional qualifications include: - Experience with static timing analysis tools, custom analog ...
Physical Design Engineer
Hillsboro, OR · On-site
$148K - $152K/yr
Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... Additional qualifications include: - Experience with static timing analysis tools, custom analog ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Minimum Qualifications BS degree in technical discipline with minimum 10 years of ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
... synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...
Principal ASIC Physical Design Engineer
OR · On-site +1
$190K - $280K/yr
... synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Preferred Qualifications This position requires detailed knowledge of the ASIC ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... timing analysis. Preferred Qualifications This position requires detailed knowledge of the ASIC ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
... and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical ... At least 8 years of experience in Physical Design and STA review.. * At least 8 years of experience ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
... and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical ... At least 8 years of experience in Physical Design and STA review.. * At least 8 years of experience ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... STA and/or Timing Closure. Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... STA and/or Timing Closure. Programming skills with Perl and TCL.
Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$170K - $272K/yr
Provide technical guidance to junior engineers. * Turn abstract concepts and customer requirements ... Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ...
Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$170K - $272K/yr
Provide technical guidance to junior engineers. * Turn abstract concepts and customer requirements ... Experience with Static Timing Analysis of ASICs or FPGAs. * Experience with digital simulation ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... analysis of timing paths to identify key issues. - Implement timing infrastructure. Preferred ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
The Role and Impact As a Physical Design Timing Engineer, you will play a critical role in ... static timing analysis, timing constraint generation, and timing optimization techniques ...
The Role and Impact As a Physical Design Timing Engineer, you will play a critical role in ... static timing analysis, timing constraint generation, and timing optimization techniques ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
Circuit Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$142K - $263K/yr
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus. Minimum ...
EDA Tools Hardware Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Static timing analysis (STA) * Power grid design and IR drop concepts * Experience with large SoC ...
EDA Tools Hardware Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Static timing analysis (STA) * Power grid design and IR drop concepts * Experience with large SoC ...
Senior/Principal Physical Design Engineer (remote)
Portland, OR · Remote
$144K - $148K/yr
Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints. * Provide technical guidance and mentoring to other engineers and ...
Quick apply
Senior/Principal Physical Design Engineer (remote)
Portland, OR · Remote
$144K - $148K/yr
Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints. * Provide technical guidance and mentoring to other engineers and ...
We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic ... Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing ...
We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic ... Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing ...
Sta Static Timing Analysis Engineer information
What is a STA static timing analysis engineer?
STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.
What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?
To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
What are some common challenges faced by STA static timing analysis engineers during project cycles?
STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.
What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Oregon?
For Sta Static Timing Analysis Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Sta Static Timing Analysis Engineer jobs in Oregon look for?
The top searched job categories for Sta Static Timing Analysis Engineer jobs in Oregon are:
What cities in Oregon are hiring for Sta Static Timing Analysis Engineer jobs?
Cities in Oregon with the most Sta Static Timing Analysis Engineer job openings:
CPU Design Timing Engineer
Beaverton, OR • On-site
Apple
• Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 10 days ago
Apple rating
8.1
Based on 685 frontline employees who took The Breakroom Quiz
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
Experience with one of the following static timing tools: Primetime or Tempus
Experience with cross talk, noise, OCV, uncertainty, and derate methodology
Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python
Preferred Qualifications
Implementation experience on high performance CPU designs
Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
Knowledge of static timing tools and flows including how to handle multiple clock and power domains
Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology
Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
Experience with one of the following static timing tools: Primetime or Tempus
Experience with cross talk, noise, OCV, uncertainty, and derate methodology
Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python
Preferred Qualifications
Implementation experience on high performance CPU designs
Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
Knowledge of static timing tools and flows including how to handle multiple clock and power domains
Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976