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Sta Static Timing Analysis Engineer Jobs in Oregon

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...

Intel

EDA Tools Hardware Engineer

Hillsboro, OR · On-site

$141K - $269K/yr

  • Medical

  • Retirement

  • PTO

The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will ... Static timing analysis (STA) * Power grid design and IR drop concepts * Experience with large SoC ...

Apple

RTL Design Engineer

Beaverton, OR

$141K/yr

... static timing analysis, and design-for-test (DFT) SystemVerilog assertions, checkers, and advanced verification techniques Scripting languages (Perl, Python) Formal verification and low-power design ...

Apple

RTL Design Engineer

Beaverton, OR

$141K/yr

... static timing analysis, and design-for-test (DFT) SystemVerilog assertions, checkers, and advanced verification techniques Scripting languages (Perl, Python) Formal verification and low-power design ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification ...

Intel

Analog Circuit Design Engineer

Hillsboro, OR

$122K - $232K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Circuit Design Engineer, you will play a pivotal role in designing, developing, and ... Cross-disciplinary knowledge in analog integration, RTL, static timing analysis, and power grid ...

Intel Corporation

Analog Circuit Design Engineer

Hillsboro, OR · On-site

$122K - $232K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Circuit Design Engineer, you will play a pivotal role in designing, developing, and ... Cross-disciplinary knowledge in analog integration, RTL, static timing analysis, and power grid ...

Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

Tualatin, OR · On-site

$123K - $196K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We are looking for an FPGA Design Engineer with exceptional technical skills and a strong desire to ... Experience with Static Timing Analysis of ASICs or FPGAs * Experience with digital simulation ...

Intel

Senior Clock Architecture & Design Engineer

Hillsboro, OR · On-site

$141K - $269K/yr

  • Medical

  • Retirement

  • PTO

Experience in physical design, clock tree synthesis (CTS) and static timing analysis * Strong background in custom circuits, transistor-level design and spice simulations * Strong programming skills ...

Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

Tualatin, OR

$123K - $196K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We are looking for an FPGA Design Engineer withexceptional technical skills and a strong desire to ... Experience with Static Timing Analysis of ASICs or FPGAs * Experience with digital simulation ...

Apple

CPU Technology Feasibility Engineer

Beaverton, OR

$128K - $169K/yr

You will be responsible for conducting experiments and analysis on process technology in CPU ... of static timing and critical path closure techniques Minimum Qualifications Minimum BS and 10+ ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are popular job titles related to Sta Static Timing Analysis Engineer jobs in Oregon?

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Sta Static Timing Analysis Engineer jobs near you
Infographic showing various Sta Static Timing Analysis Engineer job openings in Oregon as of August 2026, with employment types broken down into 94% Full Time, and 6% Part Time. Highlights an 76% In-person, 6% Hybrid, and 18% Remote job distribution.

Physical Design Engineer

Apple

Beaverton, OR • On-site

$141K - $145K/yr

Full-time

Re-posted 27 days ago

Apple rating

8.0

Company rating: 8.0 out of 10

Based on 677 frontline employees who took The Breakroom Quiz

7th of 30 rated technology retailers

Job description

At Apple we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing, and logic design teams, with a critical impact on delivering outstanding PHY designs. You will be required to do physical designs of outstanding PHY design.
Description
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Build full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
Minimum Qualifications
Bachelors of Science in Electrical Engineering and 10+ years experience preferred.
Preferred Qualifications
Deep design experience in high PHY and/or SOC designs.
Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route.
Experience in developing and implementing Power-grid and Clock specifications.
Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools.
Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools.
Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

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