ZipRecruiter

Log In

1

Soc Design Verification Engineer Jobs (NOW HIRING)

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

K-Tek Resourcing LLC

Design Verification Engineer

Sunnyvale, CA · On-site

$161K - $197K/yr

Title - Design Verification Engineer -Performance Modelling Location - Sunnyvale CA, Austin TX or ... Experience with CPU, GPU, AI/ML, Multimedia, Interconnect, or SoC verification. * Familiarity with ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Redolent, Inc.

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ... Experience with SoC-level verification , assertion-based verification , or formal verification

Altera

Design Verification Engineer

San Jose, CA · On-site

$100K - $120K/yr

Develop and execute block-level and subsystem-level verification plans for complex FPGA and SoC ... engineering productivity. * Participate in design reviews, verification reviews, and bug triage ...

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years ... SoC level testing Develop directed and random testcases, perform coverage analysis, and close ...

next page

Showing results 1-20

All JobsSoc Design Verification Engineer Jobs

Soc Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do soc design verification engineer jobs pay per year?

As of Jul 17, 2026, the average yearly pay for soc design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by SoC Design Verification Engineers during the verification process?

SoC Design Verification Engineers often encounter challenges related to the increasing complexity of modern system-on-chip architectures, such as integrating numerous IP blocks and ensuring robust communication between them. Debugging failures in large-scale simulations and managing tight project deadlines can also be demanding. Additionally, adapting to evolving verification methodologies and tools, as well as collaborating effectively with design and firmware teams to resolve issues quickly, are common aspects of the role. Successful engineers leverage strong problem-solving skills and proactive communication to navigate these challenges.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Engineer, and why are they important?

To thrive as an SoC Design Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, typically supported by a degree in electrical or computer engineering. Familiarity with hardware description languages (HDL) like Verilog or VHDL, verification tools such as UVM/SystemVerilog, and simulation/debugging environments is essential. Strong analytical thinking, problem-solving abilities, and effective communication skills help in collaborating with design teams and troubleshooting complex issues. These skills and qualities are vital to ensure the reliability, functionality, and timely delivery of complex system-on-chip products.

What are SoC Design Verification Engineers?

SoC (System-on-Chip) Design Verification Engineers are professionals who ensure that integrated circuits, which combine multiple components onto a single chip, function correctly according to their specifications. They use various verification methodologies and tools to simulate, test, and debug the design before it is manufactured. Their work involves creating testbenches, running simulation tests, and collaborating with design engineers to identify and resolve issues early in the development cycle. This helps prevent costly errors and ensures the final product meets quality and performance standards.

What is the difference between Soc Design Verification Engineer vs Soc Validation Engineer?

AspectSoc Design Verification EngineerSoc Validation Engineer
Primary FocusVerifying design correctness through simulation and testing during developmentValidating the final product to ensure it meets specifications and functions in real-world scenarios
Work EnvironmentDesign teams, simulation labs, hardware testingProduct testing, field testing, customer environments
Required CredentialsBachelor's or master's in Electrical Engineering, VLSI, or related fields; knowledge of verification toolsBachelor's or master's in Electrical Engineering, VLSI, or related fields; experience with testing methodologies

The Soc Design Verification Engineer primarily focuses on verifying the design correctness during development, while the Soc Validation Engineer tests the final product to ensure it functions correctly in real-world conditions. Both roles require similar educational backgrounds and industry experience, but their responsibilities differ in the development lifecycle.

More about Soc Design Verification Engineer jobs
What cities are hiring for Soc Design Verification Engineer jobs? Cities with the most Soc Design Verification Engineer job openings:
What states have the most Soc Design Verification Engineer jobs? States with the most job openings for Soc Design Verification Engineer jobs include:
What job categories do people searching Soc Design Verification Engineer jobs look for? The top searched job categories for Soc Design Verification Engineer jobs are:
Soc Design Verification Engineer jobs near you

Design Verification Engineer

Futran Tech Solutions Pvt. Ltd.

San Jose, CA • On-site

$158K - $192K/yr

Full-time

Posted 14 days ago

Job description

Job Title: Design Verification Engineer
Location: San Jose, CA
Contract Term: Fulltime
Job Description:
  • We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:
  • Develop and maintain UVM-based verification environments
  • Create test plans, testcases, and coverage models
  • Perform functional verification of RTL designs
  • Debug RTL and testbench issues
  • Drive coverage closure (functional + code)

Required Skills:
  • Strong hands-on with System Verilog and UVM
  • Experience in block-level verification
  • Good understanding of digital design fundamentals
  • Experience with debug tools (Verdi, DVE, etc.)

Good to Have:
  • Exposure to low-power verification (UPF)
  • Experience with AMBA protocols (AXI/AHB/APB)

Apply