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Senior Analog Layout Engineer Jobs (NOW HIRING)

Marvell

Senior Analog Layout Manager

San Diego, CA · On-site

Central System Engineering (CSE) in Central Engineering, independent of other CE functions ... Minimum 10+ years in analog layout design and 3+ years in management. * Deep understanding of ...

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Description Job Title: Sr. Analog Design Engineer Job Duties: * Conduct design and development of ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Job Title: Sr. Analog Design Engineer Job Duties: * Conduct design and development of image sensor ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

Capgemini

Analog Layout Engineer

Santa Clara, CA · On-site

$98 - $204/hr

Bachelor's degree in Electrical Engineering, Electronics, or a related field.* 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred).* Proven experience with analog ...

New

Capgemini

Analog Layout Engineer

San Francisco, CA · On-site

$98 - $204/hr

Bachelor's degree in Electrical Engineering, Electronics, or a related field.* 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred).* Proven experience with analog ...

New

Micron

Sr. Analog Design Engineer - HBM

Richardson, TX · On-site

$183K/yr

We are seeking a Senior Analog Design Engineer to join our High Bandwidth Memory (HBM) team. This ... Work closely with layout engineers to definefloorplanningand symmetry requirements,ensure matching ...

Renesas Electronics

Senior Analog Engineer

San Jose, CA · On-site

$122K - $168K/yr

We are seeking a highly motivated Senior Analog Engineer to join our Analog Design team. In this ... Layout & Physical Design Support: Support IC floorplanning and work closely with layout engineers ...

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Senior Analog Layout Engineer information

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$59.5K

$126.6K

$183.5K

How much do senior analog layout engineer jobs pay per year?

As of Sep 4, 2026, the average yearly pay for senior analog layout engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What is a senior analog layout engineer?

Senior Analog Layout Engineers are experienced professionals who design and implement the physical layout of analog integrated circuits (ICs) such as amplifiers, data converters, and power management chips. They translate circuit schematics into detailed layouts that ensure optimal electrical performance, reliability, and manufacturability. Their responsibilities include working closely with circuit designers, performing layout-versus-schematic (LVS) checks, and using specialized Electronic Design Automation (EDA) tools. Senior engineers often mentor junior staff and help resolve complex layout challenges. Their expertise is critical in ensuring the final chip meets specifications and industry standards.

What are the key skills and qualifications needed to thrive as a senior analog layout engineer?

To thrive as a Senior Analog Layout Engineer, you need deep knowledge of analog/mixed-signal IC layout, semiconductor device physics, and experience with advanced CMOS processes, typically supported by a relevant engineering degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification systems is essential. Attention to detail, problem-solving, and strong collaboration skills set standout professionals apart in this role. These abilities ensure high-performance, reliable chip designs that meet stringent industry standards and project timelines.

What are some common challenges senior analog layout engineers face when collaborating with circuit designers, and how can they be addressed?

Senior Analog Layout Engineers often encounter challenges such as translating complex circuit schematics into efficient physical layouts while meeting stringent performance requirements. Miscommunications or differing priorities between layout engineers and circuit designers can lead to design iterations or delays. To address these challenges, it’s important to establish clear communication channels, participate in regular design reviews, and use collaborative tools for feedback and issue tracking. Being proactive in discussing layout constraints and providing early feedback can help ensure that both layout and performance goals are achieved efficiently.

What is the difference between Senior Analog Layout Engineer vs Analog IC Design Engineer?

AspectSenior Analog Layout EngineerAnalog IC Design Engineer
Primary FocusPhysical layout and implementation of analog circuitsDesign and simulation of analog circuits
Skills RequiredLayout tools, fabrication process knowledge, circuit understandingCircuit theory, schematic design, simulation skills
Work EnvironmentFoundries, semiconductor companies, R&D labsDesign teams, R&D departments, EDA tool usage
Common UsageInvolved in physical design phaseInvolved in circuit conceptualization and schematic design

While both roles require a strong understanding of analog circuits, the Senior Analog Layout Engineer focuses on translating circuit schematics into physical layouts, ensuring manufacturability and performance. In contrast, the Analog IC Design Engineer primarily designs and simulates the circuits themselves. Both roles often collaborate but differ in their core responsibilities and skill sets.

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Senior Analog Layout Engineer jobs near you

Senior Analog Layout Manager

Marvell

San Diego, CA • On-site

Full-time

Life, Retirement

Re-posted 7 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.
This is a rare foundational technical management opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.

What You Can Expect

  • Hire and lead a team of layout designers.

  • Assess schedules, floor plans, and risks for digital macros.

  • Perform hands-on work at the macro level layout.

  • Manage and track layout schedules; hire additional designers as needed.

  • Assess risks and plan workarounds to meet or exceed layout schedules.

  • Identify and prioritize project tasks and risks.

  • Work with CAD, tech, and circuit design teams to synchronize layout schedules with overall project plans.

  • Understand complex layout design concepts and communicate issues cross-functionally.

What We're Looking For

  • Minimum 10+ years in analog layout design and 3+ years in management.

  • Deep understanding of layout methodology from initial chip planning to tape-out.

  • Experience with advanced process technology and FinFET is preferable.

  • High proficiency in LVS, DRC debugging, and interpreting CALIBRE DRC, ERC, LVS reports.

  • Proficient in Synopsys or CADENCE layout entry tools; programming skills in Skill, Ample, or Perl are a plus.

  • Strong technical and analytical background with excellent problem-solving skills.

  • Excellent verbal and written communication skills; experience in conflict resolution and consensus building.

  • Proven ability to build and develop a world-class analog layout team; proactive, self-starter with strong organizational skills.

Expected Base Pay Range (USD)

138,200 - 204,460, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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