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Senior Analog Layout Engineer Jobs (NOW HIRING)

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Description Job Title: Sr. Analog Design Engineer Job Duties: * Conduct design and development of ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

Marvell

Senior Analog Layout Manager

San Diego, CA

Central System Engineering (CSE) in Central Engineering, independent of other CE functions ... Minimum 10+ years in analog layout design and 3+ years in management. * Deep understanding of ...

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA

$156K - $160K/yr

Job Title: Sr. Analog Design Engineer Job Duties: * Conduct design and development of image sensor ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

Job Title: Sr. Analog Design Engineer Job Duties: * Conduct design and development of image sensor ... Collaborate with layout engineer on whole chip layout integration, verification, and improvement.

Apply Early

Apton Inc

Analog Layout Design Engineer

Cupertino, CA · On-site

$249K/yr

Analog Layout Design Engineer We are currently looking for an Analog Layout Design Engineer for an onsite position in California with one of our clients. Based on your background, I wanted to reach ...

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Senior Analog Layout Engineer information

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$59.5K

$126.6K

$183.5K

How much do senior analog layout engineer jobs pay per year?

As of Jul 5, 2026, the average yearly pay for senior analog layout engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are some common challenges Senior Analog Layout Engineers face when collaborating with circuit designers, and how can they be addressed?

Senior Analog Layout Engineers often encounter challenges such as translating complex circuit schematics into efficient physical layouts while meeting stringent performance requirements. Miscommunications or differing priorities between layout engineers and circuit designers can lead to design iterations or delays. To address these challenges, it’s important to establish clear communication channels, participate in regular design reviews, and use collaborative tools for feedback and issue tracking. Being proactive in discussing layout constraints and providing early feedback can help ensure that both layout and performance goals are achieved efficiently.

What are Senior Analog Layout Engineers?

Senior Analog Layout Engineers are experienced professionals who design and implement the physical layout of analog integrated circuits (ICs) such as amplifiers, data converters, and power management chips. They translate circuit schematics into detailed layouts that ensure optimal electrical performance, reliability, and manufacturability. Their responsibilities include working closely with circuit designers, performing layout-versus-schematic (LVS) checks, and using specialized Electronic Design Automation (EDA) tools. Senior engineers often mentor junior staff and help resolve complex layout challenges. Their expertise is critical in ensuring the final chip meets specifications and industry standards.

What is the difference between Senior Analog Layout Engineer vs Analog IC Design Engineer?

AspectSenior Analog Layout EngineerAnalog IC Design Engineer
Primary FocusPhysical layout and implementation of analog circuitsDesign and simulation of analog circuits
Skills RequiredLayout tools, fabrication process knowledge, circuit understandingCircuit theory, schematic design, simulation skills
Work EnvironmentFoundries, semiconductor companies, R&D labsDesign teams, R&D departments, EDA tool usage
Common UsageInvolved in physical design phaseInvolved in circuit conceptualization and schematic design

While both roles require a strong understanding of analog circuits, the Senior Analog Layout Engineer focuses on translating circuit schematics into physical layouts, ensuring manufacturability and performance. In contrast, the Analog IC Design Engineer primarily designs and simulates the circuits themselves. Both roles often collaborate but differ in their core responsibilities and skill sets.

What are the key skills and qualifications needed to thrive as a Senior Analog Layout Engineer, and why are they important?

To thrive as a Senior Analog Layout Engineer, you need deep knowledge of analog/mixed-signal IC layout, semiconductor device physics, and experience with advanced CMOS processes, typically supported by a relevant engineering degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification systems is essential. Attention to detail, problem-solving, and strong collaboration skills set standout professionals apart in this role. These abilities ensure high-performance, reliable chip designs that meet stringent industry standards and project timelines.
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Senior Analog Layout Engineer jobs near you
Senior Manager, Analog Layout Design

Senior Manager, Analog Layout Design

Marvell Technology, Inc.

Santa Clara, CA • On-site

Full-time

Life, Retirement

Posted 27 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As an Analog Layout Manager with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Data Center, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.
What You Can Expect
We are seeking an experienced Analog Layout Senior Manager to lead and grow a team of analog layout engineers responsible for delivering high-quality physical layout solutions for high-speed, mixed-signal, and advanced technology integrated circuits products. This role combines technical leadership, people management, project execution, and methodology development to ensure successful delivery of complex semiconductor products across multiple technology nodes and product generations.
The ideal candidate possesses deep expertise in analog and mixed-signal layout design, strong leadership skills, and a proven track record of delivering successful tapeouts in advanced process technologies.
Team Leadership and People Management
  • Lead, mentor, and develop a high-performing team of analog layout engineers through technical coaching, performance management, career development, and succession planning.
  • Foster a culture of ownership, accountability, collaboration, innovation, and technical excellence.
  • Drive hiring, onboarding, retention, and growth of top engineering talent while developing future technical and organizational leaders.
  • Provide clear direction, motivation, and support to enable team success and continuous professional development.

Project Execution and Delivery
  • Own layout execution planning, resource allocation, schedule management, and quality delivery across multiple projects.
  • Ensure timely completion of layout milestones while maintaining high standards of quality and design integrity.
  • Partner with program management and engineering leadership to identify risks, establish priorities, and drive project execution.

Technical Leadership
  • Provide technical guidance for analog and mixed-signal layout implementation in advanced technologies, including FinFET, CMOS and BiCMOS processes.
  • Oversee layout development for high-speed and mixed-signal circuits.
  • Lead layout reviews to ensure compliance with design requirements, foundry rules, reliability standards, and industry best practices.
  • Drive robust implementation of matching, shielding, isolation, noise mitigation, electromigration, EM/IR, ESD protection, and manufacturability considerations.

Cross-Functional Collaboration
  • Collaborate closely with circuit design, physical design, CAD, verification, reliability, and program management teams throughout the product development cycle.
  • Support debugging, silicon bring-up activities, root-cause analysis, yield improvement initiatives, and post-tapeout issue resolution.
  • Facilitate effective communication and alignment across geographically distributed engineering teams.

Methodology and Continuous Improvement
  • Drive improvements in layout methodologies, automation, reusable IP strategies, verification flows, and overall execution efficiency.
  • Establish and maintain layout design standards, review processes, checklists, and best practices.
  • Evaluate and deploy new EDA technologies, tools, and workflow enhancements to improve efficiency and design quality.
  • Stay current with emerging semiconductor technologies, industry trends, and layout methodologies.

What We're Looking For
  • Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field.
  • 10+ years of analog layout design experience, including 3+ years in a leadership role managing teams, projects, or technical execution.
  • Strong hands-on expertise in advanced analog, high-speed, and mixed-signal layout design, with experience in circuits such as SerDes, PLLs, ADCs/DACs, TIAs, drivers, clocking, power management, and other mixed-signal blocks.
  • Deep understanding of semiconductor devices, process technologies, parasitics, matching, shielding, isolation, reliability, manufacturability, and physical design best practices.
  • Proficiency with industry-standard EDA tools, including Cadence Virtuoso, Calibre, PVS, StarRC, or equivalent.
  • Experience with advanced FinFET process nodes and a proven track record of multiple successful tapeouts.
  • Demonstrated ability to lead, mentor, and scale high-performing engineering teams while driving layout methodology, automation, productivity improvements, and technical excellence.
  • Strong project management, prioritization, problem-solving, decision-making, communication, and collaboration skills, with the ability to influence and work effectively across cross-functional and global engineering teams.

Expected Base Pay Range (USD)
136,620 - 204,700, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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