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Senior Analog Layout Engineer Jobs in Utah (NOW HIRING)

PDF Solutions

Senior Layout Extraction Engineer

Midvale, UT · On-site

$120K - $160K/yr

The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong initiative and communication skills and possesses the drive to deliver quality results on time in a ...

PDF Solutions

Senior Layout Extraction Engineer

Midvale, UT · On-site

$120K - $160K/yr

The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong initiative and communication skills and possesses the drive to deliver quality results on time in a ...

Raytheon

Senior Motor Controls Engineer

Provo, UT

$98K - $135K/yr

What You Will Do Raytheon's Effector Analog & Power (EAP) Team is looking for mid-career engineers ... Guide ECAD drafters through layout and routing activities, with moderate support from senior ...

PassiveLogic

Senior Electrical Engineer

Salt Lake City, UT · On-site

$103K - $135K/yr

Are you driven to engineer a sustainable future? Do you possess deep electrical engineering skills ... analog design * Sharp high-speed digital design skills (signal integrity, grounding, noise, layout ...

Raytheon

Sr. Power Electronics Engineer

Provo, UT

$101K - $125K/yr

As a Senior Power & Analog Design Engineer, your responsibilities will include the following: * Lead the design, analysis, test, and/or documentation of electronic circuits. * Plan and execute ...

Raytheon

Motor Controls Engineer II

Provo, UT

$79K - $102K/yr

Guide ECAD drafters through layout and routing activities, with moderate support from senior ... Experience with analog electronics design, including at least one of the following: FETs/BJTs, op ...

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Senior Analog Layout Engineer information

What are some common challenges senior analog layout engineers face when collaborating with circuit designers, and how can they be addressed?

Senior Analog Layout Engineers often encounter challenges such as translating complex circuit schematics into efficient physical layouts while meeting stringent performance requirements. Miscommunications or differing priorities between layout engineers and circuit designers can lead to design iterations or delays. To address these challenges, it’s important to establish clear communication channels, participate in regular design reviews, and use collaborative tools for feedback and issue tracking. Being proactive in discussing layout constraints and providing early feedback can help ensure that both layout and performance goals are achieved efficiently.

What is a senior analog layout engineer?

Senior Analog Layout Engineers are experienced professionals who design and implement the physical layout of analog integrated circuits (ICs) such as amplifiers, data converters, and power management chips. They translate circuit schematics into detailed layouts that ensure optimal electrical performance, reliability, and manufacturability. Their responsibilities include working closely with circuit designers, performing layout-versus-schematic (LVS) checks, and using specialized Electronic Design Automation (EDA) tools. Senior engineers often mentor junior staff and help resolve complex layout challenges. Their expertise is critical in ensuring the final chip meets specifications and industry standards.

What is the difference between Senior Analog Layout Engineer vs Analog IC Design Engineer?

AspectSenior Analog Layout EngineerAnalog IC Design Engineer
Primary FocusPhysical layout and implementation of analog circuitsDesign and simulation of analog circuits
Skills RequiredLayout tools, fabrication process knowledge, circuit understandingCircuit theory, schematic design, simulation skills
Work EnvironmentFoundries, semiconductor companies, R&D labsDesign teams, R&D departments, EDA tool usage
Common UsageInvolved in physical design phaseInvolved in circuit conceptualization and schematic design

While both roles require a strong understanding of analog circuits, the Senior Analog Layout Engineer focuses on translating circuit schematics into physical layouts, ensuring manufacturability and performance. In contrast, the Analog IC Design Engineer primarily designs and simulates the circuits themselves. Both roles often collaborate but differ in their core responsibilities and skill sets.

What are the key skills and qualifications needed to thrive as a senior analog layout engineer?

To thrive as a Senior Analog Layout Engineer, you need deep knowledge of analog/mixed-signal IC layout, semiconductor device physics, and experience with advanced CMOS processes, typically supported by a relevant engineering degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and DRC/LVS verification systems is essential. Attention to detail, problem-solving, and strong collaboration skills set standout professionals apart in this role. These abilities ensure high-performance, reliable chip designs that meet stringent industry standards and project timelines.

What are popular job titles related to Senior Analog Layout Engineer jobs in Utah?

For Senior Analog Layout Engineer jobs in Utah, the most frequently searched job titles are:

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The top searched job categories for Senior Analog Layout Engineer jobs in Utah are:

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Senior Analog Layout Engineer jobs near you

Senior Layout Extraction Engineer

PDF Solutions

Midvale, UT • On-site

$120K - $160K/yr

Full-time

Re-posted 17 days ago

Job description

Overview

PDF is seeking an experienced Layout (FIRE) Extraction Engineer to join the DFI team, who is responsible for Apps Support. The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong initiative and communication skills and possesses the drive to deliver quality results on time in a dynamic, multi-disciplined, intensive and highly productive small team environment.

Among the products of PDF Solutions is eprobe, an electron beam inspection machine with unique capabilities. This machine especially benefits from layout information for quality and throughput. The task is to apply the inhouse PDF layout software to extract the information needed by eprobe, ranging from simply running existing setups to make modifications, checking correctness of the results and optimizing w.r.t. throughput goals.


Responsibilities
  • Running Layout (FIRE) Extraction on client site to support onsite inspection application development.
  • Remote support Layout (FIRE) Extraction for the R&D and Demo Application development.
  • Gathering information from customers on their needs
  • Contribute to customer presentations
  • Translate abstract descriptions of geometries into software configurations/scripts
  • For new software configuration, design testcases and run tests to make sure it works as intended

Qualifications

Bachelor’s Degree or higher in electrical engineering. Degrees, such as statistics or IT-related discipline may work, depending on work experience.

Skill Set

o Core Technology & Knowledge

· Theoretical and practical experience in OPC/RET (Resolution Enhancement Technology)

· Comprehensive understanding of CMOS process flow

· Knowledge of mask fabrication and design rules (DRC)

o Software/Tool Proficiency

· Experience with OPC/Mask simulation tools:

· Mentor Graphics Calibre OPC/ILT

· Synopsys Sentaurus/Litho

· ASML Brion Tachyon

· Layout processing tools:

· Cadence, Synopsys, or KLayout

· Scripting & Programming:

· Hands-on experience with Linux

· Python, Perl, Tcl, Shell scripting

· Experience in large-scale data processing and automation

o Algorithm & Data Processing Skills

· Understanding of pattern matching, shape transformation, and data optimization

· Experience in OPC optimization using Machine Learning / AI (preferred)

o Analytical & Problem-Solving Skills

· Analysis and improvement of discrepancies between layout and actual pattern

· Experience analyzing SEM/E-beam inspection data

· Experience optimizing process window (PW) and depth of focus (DOF)

o Collaboration & Work Skills

· Experience collaborating with Design, Lithography, and Fab Process teams

· Experience modifying and optimizing designs based on customer/internal feedback

· Ability to read and understand English technical papers/datasheets and write reports


Pay Range
USD $120,000.00 - USD $160,000.00 /Yr.Qualifications:

Bachelor’s Degree or higher in electrical engineering. Degrees, such as statistics or IT-related discipline may work, depending on work experience.

Skill Set

o Core Technology & Knowledge

· Theoretical and practical experience in OPC/RET (Resolution Enhancement Technology)

· Comprehensive understanding of CMOS process flow

· Knowledge of mask fabrication and design rules (DRC)

o Software/Tool Proficiency

· Experience with OPC/Mask simulation tools:

· Mentor Graphics Calibre OPC/ILT

· Synopsys Sentaurus/Litho

· ASML Brion Tachyon

· Layout processing tools:

· Cadence, Synopsys, or KLayout

· Scripting & Programming:

· Hands-on experience with Linux

· Python, Perl, Tcl, Shell scripting

· Experience in large-scale data processing and automation

o Algorithm & Data Processing Skills

· Understanding of pattern matching, shape transformation, and data optimization

· Experience in OPC optimization using Machine Learning / AI (preferred)

o Analytical & Problem-Solving Skills

· Analysis and improvement of discrepancies between layout and actual pattern

· Experience analyzing SEM/E-beam inspection data

· Experience optimizing process window (PW) and depth of focus (DOF)

o Collaboration & Work Skills

· Experience collaborating with Design, Lithography, and Fab Process teams

· Experience modifying and optimizing designs based on customer/internal feedback

· Ability to read and understand English technical papers/datasheets and write reports

Education:UNAVAILABLEEmployment Type: FULL_TIME

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