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Rtl Logic Design Intern Jobs (NOW HIRING)

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

PE Logic Design

Hillsboro, OR ยท Hybrid

$127K - $236K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

SoC Logic Design Engineer

Austin, TX ยท On-site

$141K - $200K/yr

Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and ... Conduct quality checks to ensure design integrity and readiness for physical implementation

AI System Engineer

San Jose, CA

$117K - $160K/yr

Responsible for logic design/Register-Transfer Level (RTL) entry, design quality (LINT, CDC, RDC, power, etc.), and timing closure of high-performance digital Intellectual Property (IP) * Collaborate ...

PE Logic Design

Hillsboro, OR ยท On-site

$127K - $236K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

PE Logic Design

Hillsboro, OR ยท On-site

$150 - $200/hr

As a Principal Logic Design Engineer , youwill play a pivotal role inthemicro-architecture ... Ownmicro-architecturedefinitionand RTL designfor critical blocks such as schedulers, command ...

Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and ... Conduct quality checks to ensure design integrity and readiness for physical implementation

Staff Logic Design Engineer

Milpitas, CA ยท On-site

$141K - $189K/yr

RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...

Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and ... Conduct quality checks to ensure design integrity and readiness for physical implementation

Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and ... Conduct quality checks to ensure design integrity and readiness for physical implementation

Principal Logic Design Engineer

Hillsboro, OR ยท Hybrid

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

Life at Intel As a CPU Logic Design Engineer, you will play a critical role in shaping Intel's next ... Key Responsibilities: - Develop logic design and register transfer level (RTL) coding for CPU ...

RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...

Principal Logic Design Engineer

Hillsboro, OR ยท Hybrid

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

Life at Intel As a CPU Logic Design Engineer, you will play a critical role in shaping Intel's next ... Key Responsibilities: - Develop logic design and register transfer level (RTL) coding for CPU ...

Life at Intel As a CPU Logic Design Engineer, you will play a critical role in shaping Intel's next ... Key Responsibilities: - Develop logic design and register transfer level (RTL) coding for CPU ...

Showing results 21-40

Rtl Logic Design Intern information

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$9

$19

$36

How much do rtl logic design intern jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for rtl logic design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is an RTL Logic Design intern?

RTL Logic Design Interns are students or recent graduates who assist in designing, implementing, and verifying digital circuits at the Register Transfer Level (RTL) using hardware description languages like Verilog or VHDL. Their work involves translating high-level functional specifications into efficient digital logic and working closely with senior engineers to create and test modules for chips or FPGAs. Interns gain hands-on experience with tools and methodologies used in the semiconductor industry, such as simulation, synthesis, and debugging. This role is ideal for those pursuing careers in digital hardware design or computer engineering.

What types of projects and tasks can an RTL Logic Design intern expect to work on during their internship?

As an RTL Logic Design Intern, you can expect to work on a variety of tasks such as writing and verifying Register Transfer Level (RTL) code using hardware description languages like Verilog or VHDL. You may assist in developing modules for digital circuits, running simulations, and debugging logic issues. Interns often collaborate closely with senior engineers, gaining exposure to the design flow, synthesis, and timing analysis. This hands-on experience provides a solid foundation in digital design and offers insight into how large-scale integrated circuits are developed in a professional environment.

What are the key skills and qualifications needed to thrive as an RTL Logic Design intern, and why are they important?

To thrive as an RTL Logic Design Intern, you need a solid understanding of digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with simulation tools such as ModelSim, synthesis tools like Synopsys Design Compiler, and version control systems is highly beneficial. Attention to detail, strong problem-solving abilities, and effective teamwork are critical soft skills for this role. These skills and qualities enable accurate, efficient design and verification of digital circuits, which are essential for developing reliable hardware products.

What is the difference between Rtl Logic Design Intern vs Digital Design Intern?

AspectRtl Logic Design InternDigital Design Intern
Required SkillsVerilog/VHDL, digital logic, hardware description languagesVerilog/VHDL, digital logic, FPGA/ASIC design
Work EnvironmentHardware design teams, semiconductor companiesHardware and FPGA development teams, electronics firms
Industry UsageASIC/FPGA chip design, hardware verificationFPGA prototyping, digital circuit development

Rtl Logic Design Intern focuses specifically on register-transfer level hardware description and logic design, often emphasizing Verilog or VHDL coding for chip development. Digital Design Intern has a broader scope, including FPGA and digital circuit development. Both roles require similar skills but differ slightly in project focus and application areas.

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Infographic showing various Rtl Logic Design Intern job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

Principal Logic Design Engineer

Hillsboro, OR โ€ข On-site

Protingent
Recruiting and Staffing Servicesย โ€ขย 51 - 200 employees

Full-time

Posted 20 days ago


Job description


Position Title: Principal Logic Design Engineer
Position Description: Protingent Staffing has an exciting Direct Hire opportunity for a Principal Logic Design Engineer with our client in Hillsboro, OR and San Jose, CA.
Job Responsibilities:
  • Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces
  • Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data
  • Collaborate closely with verification team to shape test plans and improve verification coverage
  • Work with physical design team to understand and resolve timing, power, and congestion challenges
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary
  • Provide technical support to FAE team on pre-sales customer engagements
  • Provide technical support to AE team on post-sales customer deliveries
Job Qualifications:
  • Strong System Verilog/Verilog RTL design expertise
  • Memory (HBM, LPDDR) expertise
  • Questa/Incisive/VCS simulator experience
  • Python/Perl/TCL scripting experience
  • Ability to learn quickly and work independently
  • Solid communication and project management skills
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE
Preferred Job Qualifications:
  • ASIC synthesis, timing constraint, CDC/RDC experience
  • UVM Verification experience
  • AMBA AXI or CHI design experience

Job Details:
  • Job Type: Direct Hire
  • Location: Hillsboro, OR or San Jose, CA (Hybrid 3 days a week onsite)
  • Salary: $127,400 to $287,600
About Protingent: Protingent is an award-winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation-from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We're passionate about connecting exceptional talent with meaningful opportunities and helping our clients build the future.
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