PHY RTL Design Engineer
$175K - $308K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$175K - $308K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$122K - $214K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$175K - $308K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
PHY RTL Design Engineer
$175K - $308K/yr
Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
RTL Tools & Methodology Engineer
San Jose, CA · On-site
$124K/yr
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL). * Strong background in RTL/logic design. * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS:
RTL Tools & Methodology Engineer
San Jose, CA · On-site
$124K/yr
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL). * Strong background in RTL/logic design. * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS:
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...
Staff Logic Design Engineer
Milpitas, CA · On-site
$141K - $189K/yr
RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...
Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50/hr
Solid understanding of logic design, VLSI, and transistor-level concepts * Familiar with PnR tools ... End-to-end physical design flow-from RTL handoff to final tapeout * Deep dive into timing, power ...
Physical Design Intern - CPU/AI Hardware
Austin, TX · On-site
$50/hr
Solid understanding of logic design, VLSI, and transistor-level concepts * Familiar with PnR tools ... End-to-end physical design flow-from RTL handoff to final tapeout * Deep dive into timing, power ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
Quick apply
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block ...
ASIC Design Intern
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
Quick apply
ASIC Design Intern
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
ASIC Design Intern
San Jose, CA · On-site
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
ASIC Design Intern
San Jose, CA · On-site
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
ASIC Design Intern
San Jose, CA · On-site
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
ASIC Design Intern
San Jose, CA · On-site
$35 - $45/hr
Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language. Preferred Qualifications * Advanced Education: Master's or PhD in Electrical Engineering with ...
Staff Logic Design Engineer
$141K - $189K/yr
RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...
Staff Logic Design Engineer
$141K - $189K/yr
RTL Design & Microarchitecture * Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed ... Design high-throughput data paths and control logic optimized for latency, bandwidth, and resource ...
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL). * Strong background in RTL/logic design. * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS:
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL). * Strong background in RTL/logic design. * Programming skills in Perl, Python, and TCL. ACADEMIC CREDENTIALS:
RTL Design / Digital (Logic) Design Engineer Position
Dallas, TX · On-site
$135K/yr
RTL Design / Digital (Logic) Design Engineer Locations: Bay Area , Austin, Dallas The role is related to High Bandwidth Memory (HBM). The program involves building a custom chip around the HBM piece ...
RTL Design / Digital (Logic) Design Engineer Position
Dallas, TX · On-site
$135K/yr
RTL Design / Digital (Logic) Design Engineer Locations: Bay Area , Austin, Dallas The role is related to High Bandwidth Memory (HBM). The program involves building a custom chip around the HBM piece ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
SoC Logic Design Engineer
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
Rtl Logic Design Intern information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do rtl logic design intern jobs pay per hour?
As of Jul 5, 2026, the average hourly pay for rtl logic design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.
What are RTL Logic Design Interns?
RTL Logic Design Interns are students or recent graduates who assist in designing, implementing, and verifying digital circuits at the Register Transfer Level (RTL) using hardware description languages like Verilog or VHDL. Their work involves translating high-level functional specifications into efficient digital logic and working closely with senior engineers to create and test modules for chips or FPGAs. Interns gain hands-on experience with tools and methodologies used in the semiconductor industry, such as simulation, synthesis, and debugging. This role is ideal for those pursuing careers in digital hardware design or computer engineering.
What are the key skills and qualifications needed to thrive as an RTL Logic Design Intern, and why are they important?
To thrive as an RTL Logic Design Intern, you need a solid understanding of digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with simulation tools such as ModelSim, synthesis tools like Synopsys Design Compiler, and version control systems is highly beneficial. Attention to detail, strong problem-solving abilities, and effective teamwork are critical soft skills for this role. These skills and qualities enable accurate, efficient design and verification of digital circuits, which are essential for developing reliable hardware products.
What types of projects and tasks can an RTL Logic Design Intern expect to work on during their internship?
As an RTL Logic Design Intern, you can expect to work on a variety of tasks such as writing and verifying Register Transfer Level (RTL) code using hardware description languages like Verilog or VHDL. You may assist in developing modules for digital circuits, running simulations, and debugging logic issues. Interns often collaborate closely with senior engineers, gaining exposure to the design flow, synthesis, and timing analysis. This hands-on experience provides a solid foundation in digital design and offers insight into how large-scale integrated circuits are developed in a professional environment.
What is the difference between Rtl Logic Design Intern vs Digital Design Intern?
| Aspect | Rtl Logic Design Intern | Digital Design Intern |
|---|---|---|
| Required Skills | Verilog/VHDL, digital logic, hardware description languages | Verilog/VHDL, digital logic, FPGA/ASIC design |
| Work Environment | Hardware design teams, semiconductor companies | Hardware and FPGA development teams, electronics firms |
| Industry Usage | ASIC/FPGA chip design, hardware verification | FPGA prototyping, digital circuit development |
Rtl Logic Design Intern focuses specifically on register-transfer level hardware description and logic design, often emphasizing Verilog or VHDL coding for chip development. Digital Design Intern has a broader scope, including FPGA and digital circuit development. Both roles require similar skills but differ slightly in project focus and application areas.
More about Rtl Logic Design Intern jobs
What cities are hiring for Rtl Logic Design Intern jobs? Cities with the most Rtl Logic Design Intern job openings:
What states have the most Rtl Logic Design Intern jobs? States with the most job openings for Rtl Logic Design Intern jobs include:
What job categories do people searching Rtl Logic Design Intern jobs look for? The top searched job categories for Rtl Logic Design Intern jobs are:
$175K - $308K/yr
Full-time
Medical, Dental, Retirement
Posted 6 days ago
Apple rating
8.1
Based on 666 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree +10 years of relevant experience in related field.
Strong understanding of DSP.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree +10 years of relevant experience in related field.
Strong understanding of DSP.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976