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Rtl Logic Design Intern Jobs (NOW HIRING)

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$150 - $200/hr

Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area ...

Solidigm

IP Logic Design Engineer

Rancho Cordova, CA · On-site

$105K - $164K/yr

Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis ... RTL design, logic synthesis, STA, ECO * Experience with lint tools, CDC/RDC analysis, and timing ...

Intel

CPU RTL Design Engineer

Austin, TX

$141K - $269K/yr

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...

Intel Corporation

CPU RTL Design Engineer

Austin, TX · On-site

$141K - $269K/yr

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...

Intel

CPU RTL Design Engineer

Phoenix, AZ · On-site

$141K - $269K/yr

As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

ARM

Staff RTL Design Engineer

Austin, TX · On-site

$198K - $268K/yr

Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.

ARM

Staff RTL Design Engineer

Austin, TX · Hybrid

$198K - $268K/yr

Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

SK hynix America

AI System Engineer

San Jose, CA · On-site

$155K - $215K/yr

Responsible for logic design/Register-Transfer Level (RTL) entry, design quality (LINT, CDC, RDC, power, etc.), and timing closure of high-performance digital Intellectual Property (IP) * Collaborate ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...

Apple

ASIC Design Engineer

Beaverton, OR · On-site

Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and converting them to design. Experience with multiple clock domains and asynchronous interfaces.

SK hynix

AI System Engineer

San Jose, CA · On-site

$117K - $160K/yr

Responsible for logic design/Register-Transfer Level (RTL) entry, design quality (LINT, CDC, RDC, power, etc.), and timing closure of high-performance digital Intellectual Property (IP) * Collaborate ...

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Rtl Logic Design Intern information

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How much do rtl logic design intern jobs pay per hour?

As of Sep 9, 2026, the average hourly pay for rtl logic design intern in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is an RTL Logic Design intern?

RTL Logic Design Interns are students or recent graduates who assist in designing, implementing, and verifying digital circuits at the Register Transfer Level (RTL) using hardware description languages like Verilog or VHDL. Their work involves translating high-level functional specifications into efficient digital logic and working closely with senior engineers to create and test modules for chips or FPGAs. Interns gain hands-on experience with tools and methodologies used in the semiconductor industry, such as simulation, synthesis, and debugging. This role is ideal for those pursuing careers in digital hardware design or computer engineering.

What types of projects and tasks can an RTL Logic Design intern expect to work on during their internship?

As an RTL Logic Design Intern, you can expect to work on a variety of tasks such as writing and verifying Register Transfer Level (RTL) code using hardware description languages like Verilog or VHDL. You may assist in developing modules for digital circuits, running simulations, and debugging logic issues. Interns often collaborate closely with senior engineers, gaining exposure to the design flow, synthesis, and timing analysis. This hands-on experience provides a solid foundation in digital design and offers insight into how large-scale integrated circuits are developed in a professional environment.

What are the key skills and qualifications needed to thrive as an RTL Logic Design intern, and why are they important?

To thrive as an RTL Logic Design Intern, you need a solid understanding of digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with simulation tools such as ModelSim, synthesis tools like Synopsys Design Compiler, and version control systems is highly beneficial. Attention to detail, strong problem-solving abilities, and effective teamwork are critical soft skills for this role. These skills and qualities enable accurate, efficient design and verification of digital circuits, which are essential for developing reliable hardware products.

What is the difference between Rtl Logic Design Intern vs Digital Design Intern?

AspectRtl Logic Design InternDigital Design Intern
Required SkillsVerilog/VHDL, digital logic, hardware description languagesVerilog/VHDL, digital logic, FPGA/ASIC design
Work EnvironmentHardware design teams, semiconductor companiesHardware and FPGA development teams, electronics firms
Industry UsageASIC/FPGA chip design, hardware verificationFPGA prototyping, digital circuit development

Rtl Logic Design Intern focuses specifically on register-transfer level hardware description and logic design, often emphasizing Verilog or VHDL coding for chip development. Digital Design Intern has a broader scope, including FPGA and digital circuit development. Both roles require similar skills but differ slightly in project focus and application areas.

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Rtl Logic Design Intern jobs near you
Infographic showing various Rtl Logic Design Intern job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

Principal Logic Design Engineer

Hillsboro, OR • On-site

Rambus.com
Semiconductor and Electronic Component Manufacturing • 501 - 1,000 employees
Learn more about Rambus.comexternal

$150 - $200/hr

Other

Medical, Dental, Retirement

Re-posted 15 days ago

Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next-generation high‑performance and cutting‑edge memory controllers for data centers and AI applications. This is a fast‑growing market with high demand from tier‑1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you.

Rambus offers a flexible work environment, embracing a hybrid approach for most office‑based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities
  • Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces
  • Analyze performance, power, and area (PPA) trade‑offs and drive design decisions based on quantitative data
  • Collaborate closely with verification team to shape test plans and improve verification coverage
  • Work with physical design team to understand and resolve timing, power, and congestion challenges
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary
  • Provide technical support to FAE team on pre‑sales customer engagements
  • Provide technical support to AE team on post‑sales customer deliveries
Qualifications
  • Strong System Verilog/Verilog RTL design expertise
  • Questa/Incisive/VCS simulator experience
  • Python/Perl/TCL scripting experience
  • Ability to learn quickly and work independently
  • Solid communication and project management skills
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE
Definite Plus
  • ASIC synthesis, timing constraint, CDC/RDC experience
  • UVM Verification experience
  • Memory (HBM, LPDDR) expertise
  • AMBA AXI or CHI design experience
Compensation and Benefits

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time‑off program, and gym membership.

The US salary range for this full‑time position is $127,400 to $236,600. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job‑related skills, experience, qualifications, work location and market conditions.

Equal Employment Opportunity & Inclusion

Rambus is a proud Equal Employment Opportunity and affirmative action employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work.

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