Santa Clara, CA · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
Santa Clara, CA · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
Rancho Cordova, CA · On-site
$105K - $164K/yr
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis ... RTL design, logic synthesis, STA, ECO * Experience with lint tools, CDC/RDC analysis, and timing ...
Rancho Cordova, CA · On-site
$105K - $164K/yr
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis ... RTL design, logic synthesis, STA, ECO * Experience with lint tools, CDC/RDC analysis, and timing ...
Hillsboro, OR · On-site
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
Hillsboro, OR · On-site
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis ... RTL design, logic synthesis, STA, ECO * Experience with lint tools, CDC/RDC analysis, and timing ...
Quick apply
Apply Early
Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis ... RTL design, logic synthesis, STA, ECO * Experience with lint tools, CDC/RDC analysis, and timing ...
Apply Early
Austin, TX · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Austin, TX · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Austin, TX · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
Austin, TX · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
Hillsboro, OR · On-site
$141K - $232K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... to confirm design features are thoroughly verified and address any RTL test failures with ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
$141K - $200K/yr
The experience must be in: - RTL development, System Verilog, and SoC logic integration ... simulation. - SoC design methodologies, including timing/power convergence and physical ...
Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic ... logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. * Strong communication ...
Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic ... logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. * Strong communication ...
Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic ... logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. * Strong communication ...
Writing readable high-quality RTL, synthesis, timing closure, design documentation, schematic ... logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. * Strong communication ...
Austin, TX · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Austin, TX · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Phoenix, AZ · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
Phoenix, AZ · On-site
$141K - $269K/yr
As a CPU Logic Design Engineer, you will play a critical role in designing and optimizing the logic for Intel's cutting-edge processors. You will drive the development of register transfer level (RTL ...
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
San Jose, CA · On-site
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
Austin, TX · On-site
$198K - $268K/yr
Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.
Austin, TX · On-site
$198K - $268K/yr
Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.
Austin, TX · Hybrid
$198K - $268K/yr
Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.
Austin, TX · Hybrid
$198K - $268K/yr
Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit * Using power aware design methodologies, analyzing early results from tools like RTL PowerPro.
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
Quick apply
Apply Early
$35 - $45/hr
As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL ... Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
Apply Early
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces * Analyze performance, power, and area (PPA ...
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
| Aspect | Rtl Logic Design Intern | Digital Design Intern |
|---|---|---|
| Required Skills | Verilog/VHDL, digital logic, hardware description languages | Verilog/VHDL, digital logic, FPGA/ASIC design |
| Work Environment | Hardware design teams, semiconductor companies | Hardware and FPGA development teams, electronics firms |
| Industry Usage | ASIC/FPGA chip design, hardware verification | FPGA prototyping, digital circuit development |
Rtl Logic Design Intern focuses specifically on register-transfer level hardware description and logic design, often emphasizing Verilog or VHDL coding for chip development. Digital Design Intern has a broader scope, including FPGA and digital circuit development. Both roles require similar skills but differ slightly in project focus and application areas.
$141K - $232K/yr
Full-time
Medical, Retirement, PTO
Posted 27 days ago
8.7
Based on 145 frontline employees who took The Breakroom Quiz
11th of 141 rated electronics manufacturers
The Role and Impact
Join Intel's distinguished team as an SoC Logic Design Engineer. In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions, contributing to Intel's mission of creating transformative technology that drives global innovation. As a key member of our team, you will have the opportunity to influence the architecture, design, and integration of next-generation SoCs. Your contributions will directly impact Intel's ability to deliver world-class products with optimal performance, power efficiency, and scalability, shaping the future of the semiconductor industry.
Key Responsibilities
- Develop high-quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs.
- Collaborate with architects to define and implement microarchitecture features of SoC blocks.
- Integrate and validate Intellectual Property (IP) blocks and subsystems into full-chip SoC designs.
- Perform quality checks and optimize designs to meet power, performance, area, and timing objectives, ensuring seamless production readiness.
- Review verification plans to confirm design features are thoroughly verified and address any RTL test failures with corrective measures.
- Employ secure development practices to mitigate security risks and maintain design integrity.
- Work with IP providers to integrate and validate IPs at the SoC level.
- Drive quality assurance compliance to enable efficient IP-SoC handoffs.
Minimum Qualifications
To excel in this role, you must meet the following requirements:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience
- OR Master's degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience
- OR PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience.
Experience must be in:
- Expertise in RTL development, System Verilog, and SoC logic integration.
- Proficiency in microarchitecture definition, logic design, and simulation.
- Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation.
Preferred Qualifications
Candidates with the following qualifications will have an advantage:
- Hands-on experience with Python, Perl, or other scripting languages.
- Familiarity with advanced Front-End RTL Design tools such as Lint, CDC, Synthesis, and Static Timing Analysis (STA).
- Experience in validation development, pre-silicon testing, and DFT/DFD tools.
- Knowledge of industry-standard IPs, fabrics, and UVM-based verification.
We are looking for innovators passionate about advancing technology. Embark on a career journey where your work will leave a profound impact on the future of computing. Apply now and help Intel create world-changing technology.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Manufacturing
10,000+ Employees
Santa Clara, CA, US
1968
