ZipRecruiter

Log In

2

Remote Asic Soc Design Engineer Jobs (NOW HIRING)

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$114K/yr

Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies * Develop and maintain UVM-based testbenches and functional test ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies * Develop and maintain UVM-based testbenches and functional test ...

Lockheed Martin Corporation

$123K - $169K/yr

As an ASIC & FPGA Associate Engineering Manager , you will lead and manage a team of ASIC/FPGA ... SOC / ASIC / FPGA design and verification considerations and methods. Develop and maintain good ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

In your first 6 months, you will develop and implement new SoC sub-systems for satellite ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

... for complex ASIC and SoC designs. This role requires deep technical ownership across DFT ... Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and ...

Apex Informatics

ASIC Design Verification Engineer

$139K - $169K/yr

Define and implement IP/SoC verification plans and build verification test benches for IP/sub ... Drive Design Verification to closure using defined verification metrics for test plans, functional ...

previous page

Showing results 41-60

All JobsAsic Soc Design Engineer JobsRemote Asic Soc Design Engineer Jobs

Remote Asic Soc Design Engineer information

See salary details

$94K

$150.2K

$202K

How much do remote asic soc design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for remote asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
More about Remote Asic Soc Design Engineer jobs
What cities are hiring for Remote Asic Soc Design Engineer jobs? Cities with the most Remote Asic Soc Design Engineer job openings:
What are the most commonly searched types of Asic Soc Design Engineer jobs? The most popular types of Asic Soc Design Engineer jobs are:
What states have the most Remote Asic Soc Design Engineer jobs? States with the most job openings for Remote Asic Soc Design Engineer jobs include:
What job categories do people searching Remote Asic Soc Design Engineer jobs look for? The top searched job categories for Remote Asic Soc Design Engineer jobs are:
Remote Asic Soc Design Engineer jobs near you
Infographic showing various Remote Asic Soc Design Engineer job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Sr. ASIC Verification Engineer

Tensordyne

Sunnyvale, CA • On-site, Remote

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 22 days ago

Job description

About Tensordyne:

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.

 
About the role:

As a senior member of Tensordyne's ASIC team, you will lead all phases of ASIC verification and will be responsible for the pre-silicon correctness of Tensordyne's next-generation family of processors for generative AI inference acceleration. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.

Responsibilities:

Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow.

  • Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.
  • SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)
  • Lead verification planning from architecture through tapeout.
  • Develop block-level, sub-system and full-chip verification environment and tests to implement test plans.
  • Establish reusable verification methodologies and frameworks - scale testbenches to subsystem and full chip environments
  • Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.
  • Triage and debug functional and performance issues with the design-under-test.
  • Drive verification signoff criteria and quality metrics - handle bug tracking, coverage convergence, regression failures.
  • Mentor and technically guide verification engineers helping them through test planning and verification closure.
  • Perform diagnostic and post-silicon validation tests in the lab.

Required Qualifications:

  • 4-8 years of ASIC verification experience - having taken multiple chips through the entire cycle of verification and post silicon validation
  • Expert in System Verilog, UVM, Constraint Randomization, Functional Coverage.
  • Experience in C/C++ or System-C
  • Deep understanding of object oriented programming principles, constrained random stimulus, and coverage driven verification approach.
  • Verification experience of high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes, etc.)
  • Scripting experience (Python, Perl, TCL, shell programming) highly-desirable.
  • Interest to explore AI architectures for convolution, transformer and other kinds of workloads
  • Self-starter and highly-motivated to work in a dynamic start-up environment.
  • B.S. (M.S. preferred) degree in Electrical or Computer engineering (or similar field).
 
Reasons to consider joining Tensordyne:
  • Ground floor opportunity with the team; be part of shaping one of the most exciting new companies.
  • Learning and development opportunities from a highly diverse and talented peer group, including experts in a wide range of fields, from Artificial Intelligence & Computer Vision to Systems & Device Engineering.
  • Competitive benefits package including Medical, Vision, Dental
  • Perks including meals, snacks, drinks and us!
  • Sharp, motivated co-workers in a fun office environment
  • Flexible work hours & generous PTO policy
 
Tensordyne's culture was built on the following values that are equally important to us as business:
  • Put people first. We only succeed when our people succeed.
  • Ethics and integrity always; Being open, honest, and respectful of everyone.
  • Think Big. Be ambitious and have audacious goals.
  • Aim for excellence. Quality and excellence count in everything we do.
  • Own it and get it done. Results matter!
  • Make Each Person Better together than they would be as an individual.
  • Embrace each others' differences.
  • Embrace that there will be differences.

Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

A note to Recruitment Agencies: Please don't reach out to Recogni employees or leaders about our roles -- we've got it covered. We don't accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.

Apply