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Remote Asic Soc Design Engineer Jobs (NOW HIRING)

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ... This is a remote position for employees residing within the United States. We offer a competitive ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CA ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

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How much do remote asic soc design engineer jobs pay per year?

As of Jul 19, 2026, the average yearly pay for remote asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
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Physical Design Engineer

Physical Design Engineer

Central Business Solutions

San Jose, CA • On-site, Remote

$159K - $164K/yr

Full-time

Re-posted 26 days ago

Job description

Title: Physical Design Engineer
Location: 100% Remote
Duration: Long Term Contract role
Responsibilities
  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience
  • Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
  • Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
  • Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre.

Preferred Qualification:
  • Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
  • Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
  • Experience in Block-level and Full-chip floor-planning, power grid planning
  • Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
  • Experience with Python, TCL, Perl programming.

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