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Remote Asic Soc Design Engineer Jobs (NOW HIRING)

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their ... This is a fully remote, part-time engagement requiring approximately 20-40 hours per week ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ... This is a remote position for employees residing within the United States. We offer a competitive ...

IC Enable

RTL Design Engineer

Richardson, TX · On-site +1

$122K/yr

... ASIC/SoC development flows, and the ability to collaborate across design, verification, analog ... Richardson, TX (Hybrid, Remote considered based on experience and qualifications) What You'll Do:

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... In your first 6 months, you will develop and implement new SoC sub-systems for satellite ...

IC Enable

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ... Remote Key Responsibilities * Develop, integrate, and verify Verilog RTL for digital and mixed ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... In your first 6 months, you will develop and implement new SoC sub-systems for satellite ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

S. in Electrical Engineering, Computer Engineering, or related field. * 5+ years of experience in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, and ...

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

S. in Electrical Engineering, Computer Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... ASIC/SoC development, focused on emulation * Solid understanding of SystemVerilog, digital logic ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

S. in Electrical Engineering, Computer Engineering, or related field. * 5+ years of experience in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, and ...

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How much do remote asic soc design engineer jobs pay per year?

As of Aug 29, 2026, the average yearly pay for remote asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
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Remote Asic Soc Design Engineer jobs near you
Infographic showing various Remote Asic Soc Design Engineer job openings in the United States as of August 2026, with employment types broken down into 90% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

ASIC/SoC Design & Verification Engineer

Remote

Weekday AI
See more jobs at Weekday AIexternal

$70 - $100/hr

Part-time

Re-posted yesterday

Job description

This role is for one of our clients
Compensation: $70-$100 per hour
Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.
Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.
This is a fully remote, part-time engagement requiring approximately 20-40 hours per week, depending on your availability.
Requirements
Key Responsibilities
  • Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
  • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
  • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
  • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
  • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
  • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.
Required Qualifications
  • Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
  • Strong proficiency in SystemVerilog and Verilog.
  • Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
  • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
  • Deep expertise in one or more of the following areas:
    • RTL Design and Microarchitecture
    • Functional Verification (UVM, SVA, Cocotb, testbench development)
    • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
    • Formal Verification and Coverage Closure
    • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
    • Analog/Mixed-Signal Design Verification
    • Hardware Specification Development and Technical Documentation
  • Ability to commit 20-40 hours per week with reliable weekday availability.
  • Strong written communication skills and the ability to work independently in a remote environment.
Preferred Qualifications
  • Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
  • Graduate research or industry experience in semiconductor design, verification, or computer architecture.
  • Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
  • Experience mentoring engineers or reviewing complex technical designs.
Why Join
  • Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
  • Apply your practical chip design and verification expertise to improve the next generation of AI models.
  • Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
  • Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.
Equal Opportunity
We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.
Contract & Engagement Details
  • Independent contractor engagement.
  • Fully remote with flexible working hours.
  • Expected commitment of approximately 20-40 hours per week.
  • Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
  • Work does not require access to confidential or proprietary information from any current or former employer.
  • Payments are issued weekly based on approved work completed.
  • At this time, we are unable to support H1-B or STEM OPT candidates.

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