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Asic Soc Design Engineer Jobs (NOW HIRING)

Dexian DISYS

ASIC / SoC RTL Design Engineer

San Jose, CA

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...

Dexian

ASIC / SoC RTL Design Engineer

Campbell, CA · On-site

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...

Trinity Technology Solutions

ASIC Engineer

San Jose, CA · On-site

$194K/yr

... Design Engineer to join their growing team in San Jose. This role is ideal for engineers with ... Lead ASIC/SoC architecture and micro-architecture development from concept through production

OMNIVISION

SoC Design Engineer

Santa Clara, CA

SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...

OmniVision Technologies

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156K - $160K/yr

SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Execute ASIC implementation tasks including RTL coding, simulation, synthesis, formal verification ...

Infoyogi LLC

ASIC/RTL Design Engineer

San Jose, CA

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will ... Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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Asic Soc Design Engineer information

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$202K

How much do asic soc design engineer jobs pay per year?

As of Jun 21, 2026, the average yearly pay for asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC SoC Design Engineer job?

An ASIC SoC Design Engineer is responsible for designing, developing, and verifying integrated circuits and system-on-chip (SoC) solutions. They work on various stages of chip development, including architecture specification, RTL coding, simulation, synthesis, and verification. Their role involves collaborating with hardware, software, and verification teams to optimize performance, power, and area. These engineers use hardware description languages like Verilog and VHDL, along with EDA tools for design and validation. The goal is to create efficient and high-performance ASIC or SoC solutions for applications like consumer electronics, networking, and AI.

What are some typical challenges faced by ASIC SoC Design Engineers during a project?

ASIC SoC Design Engineers often encounter challenges such as balancing strict power, performance, and area constraints while meeting tight project deadlines. Debugging complex integration issues and staying aligned with evolving specifications requires strong analytical skills and close collaboration with verification, software, and systems teams. It's common to work in fast-paced, iterative development cycles where proactive problem-solving and adaptability are essential. Overcoming these challenges not only ensures successful chip design but also provides valuable learning opportunities and growth in technical expertise.

What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position, and why are they important?

To thrive as an ASIC SoC Design Engineer, a strong background in digital design, computer architecture, and electrical engineering—typically with a bachelor's or master's degree in a related field—is essential. Mastery of hardware description languages like Verilog or VHDL, experience with EDA tools (such as Synopsys or Cadence suites), and familiarity with verification methodologies are commonly required, often enhanced by relevant certifications. Soft skills such as problem-solving, collaboration, and effective communication are vital for interfacing with cross-functional teams and managing complex projects. These competencies enable efficient design cycles, high-quality silicon solutions, and successful integration within multidisciplinary engineering environments.

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Asic Soc Design Engineer jobs near you
Infographic showing various Asic Soc Design Engineer job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 81% Physical, 6% Hybrid, and 13% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC/SoC Design Engineer

ASIC/SoC Design Engineer

Advanced Micro Devices, Inc

San Jose, CA • On-site

$145K/yr

Full-time

Posted 14 hours ago

Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

22nd of 139 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD is looking for motivated individuals seeking opportunities to solve complex problems in a fast-paced work environment. Successful candidate will be involved in the microarchitectural design and RTL implementation of Adaptive SoC and FPGA configuration system.
THE PERSON:
You are passionate about complex Adaptive SoC and FPGA Configuration solutions and thrive in environments that require cross-domain expertise. You have strong/effective communication skill, excellent analytical and problem-solving skills. You excel at collaborating across hardware and software teams and can influence architecture decisions for next-generation configuration solutions.
KEY RESPONSIBILITIES:
  • Author detailed micro-architecture specification and own RTL implementation of next-gen FPGA Configuration controller.
  • Collaborate with hardware, firmware, and software teams to ensure a robust and cohesive configuration solution.
  • Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • Integrate complex configuration blocks into full-chip environment, ensuring proper connectivity, clock domain crossings, power domain crossing
  • Partner with verification teams to ensure comprehensive functional coverage.
  • Work closely with test engineers to implement design-for-test (DFT) and special FPGA test features to reduce test time and improve coverage
  • Drive performance, power, and area (PPA) optimization for configuration/control paths
  • Work with the Physical Design team to ensure proper implementation of the design

PREFERRED EXPERIENCE:
  • Proven background experiences in ASIC design.
  • Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB)
  • Experienced with Verilog, System Verilog, SystemVerilog Assertions (SVA)
  • Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
  • Experience in industry-standard ASIC CAD tools for simulation, synthesis, STA, LINT, LEC, CDC, RDC and power estimation, etc.
  • Experience in designs with multiple power domains and UPF
  • Proficiency with scripting languages like Perl, Python and Makefile
  • System level knowledge is a plus for supporting complex customer configuration issues

ACADEMIC CREDENTIALS:
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
LOCATION: San Jose
This role is not eligible for visa sponsorship.
#LI-CJ3
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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