Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC Design Verification Engineer
$159K - $194K/yr
Experience in SoC verification cycle from architecture to tape out to bring up. * Good knowledge of verification methodologies such as UVM/OVM etc. * Hand on ASIC-SoC Design verification tests and ...
ASIC Design Verification Engineer
$159K - $194K/yr
Experience in SoC verification cycle from architecture to tape out to bring up. * Good knowledge of verification methodologies such as UVM/OVM etc. * Hand on ASIC-SoC Design verification tests and ...
FPGA Design Engineer ~ Digital Design ~ embedded systems
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
FPGA Design Engineer ~ Digital Design ~ embedded systems
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
SoC Design Engineer
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
SoC Design Engineer
$156K - $160K/yr
SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...
FPGA Design Engineer ~ Digital Design ~ embedded systems
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
FPGA Design Engineer ~ Digital Design ~ embedded systems
Cambridge, MA · On-site
$149K/yr
Experience with ASIC/SoC design and implementation flow is desired. Preferred Qualifications * Ph.D. in Electrical or Computer Engineering * Prior experience working with cryptography, signal ...
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
ASIC Design Verification Engineer
$115K - $135K/yr
Position SummaryAs a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations ...
ASIC Design Verification Engineer
$115K - $135K/yr
Position SummaryAs a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations ...
Physical Design Engineer
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Physical Design Engineer
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Wireless SoC Design Engineer
San Diego, CA · On-site
Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
Wireless SoC Design Engineer
San Diego, CA · On-site
Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
We are looking for a Senior ASIC Design Verification Engineer (L3 or L4) to contribute to the verification of complex digital and mixed-signal ASIC, SoC, subsystem, IP, and FPGA designs. This role is ...
We are looking for a Senior ASIC Design Verification Engineer (L3 or L4) to contribute to the verification of complex digital and mixed-signal ASIC, SoC, subsystem, IP, and FPGA designs. This role is ...
Principal ASIC Design Verification Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
Position SummaryAs a Principal ASIC Design Verification Engineer, you will lead verification planning and execution for complex ASIC, SoC, subsystem, and FPGA designs. You will define verification ...
Principal ASIC Design Verification Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
Position SummaryAs a Principal ASIC Design Verification Engineer, you will lead verification planning and execution for complex ASIC, SoC, subsystem, and FPGA designs. You will define verification ...
Wireless SoC Design Engineer
San Diego, CA · On-site
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred ...
Wireless SoC Design Engineer
San Diego, CA · On-site
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Knowledgeable about the ASIC design flow, including System Verilog RTL implementation. Preferred ...
Senior SOC Design Engineer
Santa Clara, CA · On-site
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
Senior SOC Design Engineer
Santa Clara, CA · On-site
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Asic Soc Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic soc design engineer jobs pay per year?
What is an ASIC SoC Design Engineer job?
An ASIC SoC Design Engineer is responsible for designing, developing, and verifying integrated circuits and system-on-chip (SoC) solutions. They work on various stages of chip development, including architecture specification, RTL coding, simulation, synthesis, and verification. Their role involves collaborating with hardware, software, and verification teams to optimize performance, power, and area. These engineers use hardware description languages like Verilog and VHDL, along with EDA tools for design and validation. The goal is to create efficient and high-performance ASIC or SoC solutions for applications like consumer electronics, networking, and AI.
What are some typical challenges faced by ASIC SoC Design Engineers during a project?
ASIC SoC Design Engineers often encounter challenges such as balancing strict power, performance, and area constraints while meeting tight project deadlines. Debugging complex integration issues and staying aligned with evolving specifications requires strong analytical skills and close collaboration with verification, software, and systems teams. It's common to work in fast-paced, iterative development cycles where proactive problem-solving and adaptability are essential. Overcoming these challenges not only ensures successful chip design but also provides valuable learning opportunities and growth in technical expertise.
What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position, and why are they important?
To thrive as an ASIC SoC Design Engineer, a strong background in digital design, computer architecture, and electrical engineering—typically with a bachelor's or master's degree in a related field—is essential. Mastery of hardware description languages like Verilog or VHDL, experience with EDA tools (such as Synopsys or Cadence suites), and familiarity with verification methodologies are commonly required, often enhanced by relevant certifications. Soft skills such as problem-solving, collaboration, and effective communication are vital for interfacing with cross-functional teams and managing complex projects. These competencies enable efficient design cycles, high-quality silicon solutions, and successful integration within multidisciplinary engineering environments.

Full-time
Medical, Retirement, PTO
Re-posted 10 days ago
Job description
TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.
We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.
Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.
Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.
Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.
Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.
Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.
Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.
Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.
Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.
MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
Experience with Verilog and system Verilog
Experience with VCS, Verdi or other industry standard tools
Experience with pre-layout simulation and post-layout simulation
Understanding of the design flow. Ability to work with the backend team
Familiarity with AMBA APB AXI Protocol
Familiarity with RISC/Arm or other core architectures
Ability to create innovative architecture and solutions to customer requirements
Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a strong plus:
FPGA/ASIC design of image processing systems
Working knowledge of SoC architecture such as CPU, GPU or accelerators
Familiarity with: UVM, place-and-route, STA, EM/IR/Power
All your information will be kept confidential according to EEO guidelines.
About TetraMem Accelerate The World
Sourced by ZipRecruiter
Industry
Computer and peripheral equipment manufacturing
Company size
11 - 50 Employees
Headquarters location
Fremont, CA, US
Year founded
2018