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Monday Through Friday Asic Soc Design Engineer Jobs

ASIC Design Engineer

San Diego, CA · On-site

$99 - $148/hr

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects ...

... taken chips through tapeout, this opportunity allows you to apply your practical engineering ... Hands-on experience in ASIC and/or SoC design , functional verification, or digital hardware ...

Senior ASIC Design Engineer Description - HP is the world's leading printing company. We are ... Very familiar with digital ASIC/SOC design flow from RTL to silicon characterization * Very ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: * Design and verify digital circuits for CMOS image sensors (CIS ... Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog ...

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job ... Develop and execute comprehensive verification plans for ASIC/SoC designs. * Build reusable UVM ...

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...

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Monday Through Friday Asic Soc Design Engineer information

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How much do monday through friday asic soc design engineer jobs pay per year?

As of Aug 30, 2026, the average yearly pay for monday through friday asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

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ASIC Chip Lead / Design Engineer

Brooklyn Park, MN • On-site

Technical Link
IT Services • 1 - 10 employees

Other

Posted 4 days ago


Job description

ASIC Chip Lead / Design EngineerJob Description

As an ASIC Chip Lead and Design Engineer, you will play a pivotal role in the development of custom-designed Application-Specific Integrated Circuits (ASICs). Your expertise will span the entire chip design lifecycle, from conceptualization through implementation.

You will collaborate with cross-functional teams to ensure successful chip development while meeting performance, power, and area targets. The ideal candidate is a highly capable, hands-on engineer currently designing complex digital blocks with strong knowledge and experience across the complete ASIC/SoC design flow.

Additional experience with radiation-hardened design, analog/mixed-signal design and EDA, and standard-cell library development is highly desirable.

Additional responsibilities include evaluating customer requirements, estimating effort and expenses for potential new business, and identifying opportunities to improve internal design methodologies.

Essential Duties & ResponsibilitiesChip Architecture & Development
  • Lead the architectural design of ASICs based on high-level requirements and block diagrams.

  • Collaborate with system architects to define chip functionality, interfaces, and performance targets.

  • Develop detailed specifications for chip components.

RTL Design & Synthesis
  • Use Synopsys Design Compiler to create and synthesize RTL designs.

  • Optimize RTL code for area, power, and performance.

  • Implement and verify complex digital blocks.

Constraint Development
  • Develop timing constraints for the entire chip.

  • Work closely with physical design teams to ensure successful place-and-route.

RISC Processor Conformance
  • Constrain and verify RISC processors within the chip.

  • Optimize processor performance and power efficiency.

Physical Design Collaboration
  • Collaborate with physical design teams on floorplanning, placement, and routing.

  • Address design closure issues throughout the development process.

Verification Support
  • Work with verification engineers to ensure functional correctness.

  • Assist with testbench development and verification of chip functionality.

Development Environment
  • Utilize modern revision-control tools and best practices within a collaborative, multi-site design environment.

  • Work proficiently within UNIX/Linux environments, including shell scripting and utilities such as sed, awk, and grep.

  • Utilize high-level programming and scripting languages such as C/C++, Perl, Python, and Tcl.

  • Work effectively with standard Windows applications, including Word, Excel, PowerPoint, Visio, and Project.

Qualifications
  • Bachelor''s or Master''s degree in Electrical Engineering, Computer Science, or a related field.

  • 10+ years of direct industry experience in ASIC and/or SoC design.

  • Strong background in RTL-based digital IC design using Verilog/SystemVerilog.

  • Proficiency with Synopsys Design Compiler and other industry-standard EDA tools.

  • Strong understanding of digital design principles and the complete ASIC/SoC design flow.

  • Familiarity with RISC architectures, such as ARM or MIPS.

  • Proven track record of first-pass silicon success.

  • Excellent problem-solving skills and strong attention to detail.

  • Self-starter with the ability to assume technical leadership responsibilities.

  • Ability to work effectively within diverse, cross-functional engineering teams.

  • Willingness and ability to mentor less experienced engineers.

  • Experience with industry-standard development tools and methodologies.

Preferred Experience
  • Radiation-hardened (rad-hard) ASIC design.

  • Analog/mixed-signal design and EDA flows.

  • Standard-cell library development.