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Asic Soc Design Engineer Jobs (NOW HIRING)

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop ...

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

We are seeking an experienced Physical Design Engineer / Lead with 10+ years of experience in ASIC/SoC physical design. The ideal candidate will have hands-on expertise in the complete RTL-to-GDSII ...

We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...

The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications Shown experience writing micro-architecture ...

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that ...

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL ...

Debug SoC Design Engineer

Irvine, CA · On-site

$146K - $178K/yr

This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with ...

Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Preferred Qualifications MSEE with some years of industry experience Shown ...

Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...

Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...

Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...

Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...

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Asic Soc Design Engineer information

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How much do asic soc design engineer jobs pay per year?

As of Jul 19, 2026, the average yearly pay for asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC SoC Design Engineer job?

An ASIC SoC Design Engineer is responsible for designing, developing, and verifying integrated circuits and system-on-chip (SoC) solutions. They work on various stages of chip development, including architecture specification, RTL coding, simulation, synthesis, and verification. Their role involves collaborating with hardware, software, and verification teams to optimize performance, power, and area. These engineers use hardware description languages like Verilog and VHDL, along with EDA tools for design and validation. The goal is to create efficient and high-performance ASIC or SoC solutions for applications like consumer electronics, networking, and AI.

What are some typical challenges faced by ASIC SoC Design Engineers during a project?

ASIC SoC Design Engineers often encounter challenges such as balancing strict power, performance, and area constraints while meeting tight project deadlines. Debugging complex integration issues and staying aligned with evolving specifications requires strong analytical skills and close collaboration with verification, software, and systems teams. It's common to work in fast-paced, iterative development cycles where proactive problem-solving and adaptability are essential. Overcoming these challenges not only ensures successful chip design but also provides valuable learning opportunities and growth in technical expertise.

What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position, and why are they important?

To thrive as an ASIC SoC Design Engineer, a strong background in digital design, computer architecture, and electrical engineering—typically with a bachelor's or master's degree in a related field—is essential. Mastery of hardware description languages like Verilog or VHDL, experience with EDA tools (such as Synopsys or Cadence suites), and familiarity with verification methodologies are commonly required, often enhanced by relevant certifications. Soft skills such as problem-solving, collaboration, and effective communication are vital for interfacing with cross-functional teams and managing complex projects. These competencies enable efficient design cycles, high-quality silicon solutions, and successful integration within multidisciplinary engineering environments.

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Infographic showing various Asic Soc Design Engineer job openings in the United States as of July 2026, with employment types broken down into 95% Full Time, 1% Part Time, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
Lead SoC Design Engineer

Lead SoC Design Engineer

Anodize

Los Altos, CA • On-site

Other

Posted 12 days ago


Job description

Summary

We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.

Responsibilities

  • Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.
  • Drive PPA targets:  Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
  • Partner with verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
  • RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.

Minimum Requirements

  • 10+ years of experience in developing complex ASICs in advanced nodes.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB).
  • Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
  • Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
  • Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
  • Experience designing with multiple power domains and UPF.

Preferred Qualifications

  • Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
  • Experience working directly with Arm cores and subsystems.