Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ... Skilled in defining ASIC microarchitecture to meet functional requirements while managing ...
Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute
Milpitas, CA · Remote
$95 - $100/hr
ASIC/SoC Design Qualification and Education: * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related technical field. Founded in 2010 and ...
Quick apply
Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute
Milpitas, CA · Remote
$95 - $100/hr
ASIC/SoC Design Qualification and Education: * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related technical field. Founded in 2010 and ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software ...
Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
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Senior FPGA Design Engineer
Chandler, AZ · On-site
$101K - $136K/yr
Strong digital design engineer with FPGA/ASIC SoC design experience * Strong FPGA Implementation with Altera Quartus or Xilinx Vivado * Experience designing/debugging SoC systems with AMBA-compliant ...
Physical Design Engineer
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Physical Design Engineer
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Senior Physical Design / STA Engineer Location: Bay Area, CA / Austin, TX - CA 1st preference ... ASIC/SoC designs. Responsibilities * Perform full-chip and block-level physical design ...
Senior Physical Design / STA Engineer Location: Bay Area, CA / Austin, TX - CA 1st preference ... ASIC/SoC designs. Responsibilities * Perform full-chip and block-level physical design ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sunnyvale, CA · On-site
$175K - $280K/yr
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Wireless SoC Design Engineer
$171K - $302K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$171K - $302K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$120K - $210K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
Wireless SoC Design Engineer
$120K - $210K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
Asic Soc Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic soc design engineer jobs pay per year?
As of Jun 21, 2026, the average yearly pay for asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What is an ASIC SoC Design Engineer job?
An ASIC SoC Design Engineer is responsible for designing, developing, and verifying integrated circuits and system-on-chip (SoC) solutions. They work on various stages of chip development, including architecture specification, RTL coding, simulation, synthesis, and verification. Their role involves collaborating with hardware, software, and verification teams to optimize performance, power, and area. These engineers use hardware description languages like Verilog and VHDL, along with EDA tools for design and validation. The goal is to create efficient and high-performance ASIC or SoC solutions for applications like consumer electronics, networking, and AI.
What are some typical challenges faced by ASIC SoC Design Engineers during a project?
ASIC SoC Design Engineers often encounter challenges such as balancing strict power, performance, and area constraints while meeting tight project deadlines. Debugging complex integration issues and staying aligned with evolving specifications requires strong analytical skills and close collaboration with verification, software, and systems teams. It's common to work in fast-paced, iterative development cycles where proactive problem-solving and adaptability are essential. Overcoming these challenges not only ensures successful chip design but also provides valuable learning opportunities and growth in technical expertise.
What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position, and why are they important?
To thrive as an ASIC SoC Design Engineer, a strong background in digital design, computer architecture, and electrical engineering—typically with a bachelor's or master's degree in a related field—is essential. Mastery of hardware description languages like Verilog or VHDL, experience with EDA tools (such as Synopsys or Cadence suites), and familiarity with verification methodologies are commonly required, often enhanced by relevant certifications. Soft skills such as problem-solving, collaboration, and effective communication are vital for interfacing with cross-functional teams and managing complex projects. These competencies enable efficient design cycles, high-quality silicon solutions, and successful integration within multidisciplinary engineering environments.
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What are the most commonly searched types of Asic Soc Design Engineer jobs? The most popular types of Asic Soc Design Engineer jobs are:
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Apple rating
8.1
Based on 662 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.
Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases-from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Bachelors Degree in EE,CE, or related field.Knowledgeable about the ASIC design flow, including System Verilog RTL implementation.
Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.Knowledgeable in Lint, CDC, RDC, Synthesis and STA.Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI.Thorough understanding of cross clock-domain design principles and associated CDC requirements.Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis.Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.Strong communication skills, both written and oral.
Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases-from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Bachelors Degree in EE,CE, or related field.Knowledgeable about the ASIC design flow, including System Verilog RTL implementation.
Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.Knowledgeable in Lint, CDC, RDC, Synthesis and STA.Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI.Thorough understanding of cross clock-domain design principles and associated CDC requirements.Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis.Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.Strong communication skills, both written and oral.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976