All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
ASIC/SoC Design Verification Engineer
$110K - $300K/yr
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification * Build and maintain infrastructure/environment for automation ...
ASIC/SoC Design Verification Engineer
$110K - $300K/yr
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification * Build and maintain infrastructure/environment for automation ...
Physical Design Engineer
San Jose, CA · On-site
$159.40K - $164.10K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Physical Design Engineer
San Jose, CA · On-site
$159.40K - $164.10K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
Wireless SoC Design Engineer
$120.30K - $210.10K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
Wireless SoC Design Engineer
$120.30K - $210.10K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178.20K/yr
This is a highly visible role, where you will be at the center of the ASIC debug efforts ... Knowledge of digital design, SoC architecture, and HDL languages like Verilog.Familiarity with ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
Wireless SoC Design Engineer
$120.30K - $210.10K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
Wireless SoC Design Engineer
$120.30K - $210.10K/yr
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. Familiarity with ASIC test methodologies ...
Wireless SoC Design Engineer
San Diego, CA · On-site
$171.60K - $302.20K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
San Diego, CA · On-site
$171.60K - $302.20K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$171.60K - $302.20K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$139.50K - $258.10K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Wireless SoC Design Engineer
$139.50K - $258.10K/yr
Our wireless SOC organization is responsible for all aspects of wireless silicon development. With ... Familiarity with ASIC low power design techniques, including multiple supply domains configuration ...
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
Quick apply
Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
Digital ASIC Design Engineer
San Diego, CA · On-site
$98.50K - $147.70K/yr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and ...
Digital ASIC Design Engineer
San Diego, CA · On-site
$98.50K - $147.70K/yr
As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and ...
PCIe ASIC Design Engineer
San Jose, CA · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
PCIe ASIC Design Engineer
San Jose, CA · On-site
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... in ASIC/SoC design with a focus on PCIe controller integration. * Proven experience in silicon ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification. * Build and maintain infrastructure/environment for automation ...
Staff Digital Design Engineer
San Diego, CA · On-site
$139K - $232.18K/yr
... ASIC/SoC development, including RTL design, verification, subsystem integration, and silicon ... Develop and implement engineering change orders (ECOs) * Participate in system bring-up, validation ...
Staff Digital Design Engineer
San Diego, CA · On-site
$139K - $232.18K/yr
... ASIC/SoC development, including RTL design, verification, subsystem integration, and silicon ... Develop and implement engineering change orders (ECOs) * Participate in system bring-up, validation ...
Asic Soc Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic soc design engineer jobs pay per year?
As of May 31, 2026, the average yearly pay for asic soc design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What is an ASIC SoC Design Engineer job?
An ASIC SoC Design Engineer is responsible for designing, developing, and verifying integrated circuits and system-on-chip (SoC) solutions. They work on various stages of chip development, including architecture specification, RTL coding, simulation, synthesis, and verification. Their role involves collaborating with hardware, software, and verification teams to optimize performance, power, and area. These engineers use hardware description languages like Verilog and VHDL, along with EDA tools for design and validation. The goal is to create efficient and high-performance ASIC or SoC solutions for applications like consumer electronics, networking, and AI.
What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position, and why are they important?
To thrive as an ASIC SoC Design Engineer, a strong background in digital design, computer architecture, and electrical engineering—typically with a bachelor's or master's degree in a related field—is essential. Mastery of hardware description languages like Verilog or VHDL, experience with EDA tools (such as Synopsys or Cadence suites), and familiarity with verification methodologies are commonly required, often enhanced by relevant certifications. Soft skills such as problem-solving, collaboration, and effective communication are vital for interfacing with cross-functional teams and managing complex projects. These competencies enable efficient design cycles, high-quality silicon solutions, and successful integration within multidisciplinary engineering environments.
What are some typical challenges faced by ASIC SoC Design Engineers during a project?
ASIC SoC Design Engineers often encounter challenges such as balancing strict power, performance, and area constraints while meeting tight project deadlines. Debugging complex integration issues and staying aligned with evolving specifications requires strong analytical skills and close collaboration with verification, software, and systems teams. It's common to work in fast-paced, iterative development cycles where proactive problem-solving and adaptability are essential. Overcoming these challenges not only ensures successful chip design but also provides valuable learning opportunities and growth in technical expertise.
More about Asic Soc Design Engineer jobs
- What are some typical challenges faced by ASIC SoC Design Engineers during a project?
- What are the key skills and qualifications needed to thrive in the Asic Soc Design Engineer position and why are they important?
- What is an ASIC SoC Design Engineer job?
- The 10 Top Types Of Asic Soc Design Engineer Jobs
What cities are hiring for Asic Soc Design Engineer jobs? Cities with the most Asic Soc Design Engineer job openings:
What are the most commonly searched types of Asic Soc Design Engineer jobs? The most popular types of Asic Soc Design Engineer jobs are:
What job categories do people searching Asic Soc Design Engineer jobs look for? The top searched job categories for Asic Soc Design Engineer jobs are:
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum requirement of a bachelors degree.Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
MSEE with some years of industry experience Shown experience writing micro-architecture specifications and converting them to design Exposure to design methodologies and industry standard EDA tools.Experience with AXI/AHB bus fabric and processor sub-systems.Understanding of UPF and low-power design & implementation techniques.Self-starter and willingness to learn.
In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.
Minimum requirement of a bachelors degree.Familiarity with the ASIC design flow.Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
MSEE with some years of industry experience Shown experience writing micro-architecture specifications and converting them to design Exposure to design methodologies and industry standard EDA tools.Experience with AXI/AHB bus fabric and processor sub-systems.Understanding of UPF and low-power design & implementation techniques.Self-starter and willingness to learn.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976