Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to ...
Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to ...
Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to ...
Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory circuit innovation, test-chip design. * Pre-Si verification, post-Si validation and debugging to ...
Memory bit-cell and complex periphery IC layout and automation.* Memory array/IP design, memory circuit innovation, test-chip design.* Pre-Si verification, post-Si validation and debugging to enable ...
Memory bit-cell and complex periphery IC layout and automation.* Memory array/IP design, memory circuit innovation, test-chip design.* Pre-Si verification, post-Si validation and debugging to enable ...
Senior SoC Physical Design & Verification Engineer
Beaverton, OR · On-site
$143K - $147K/yr
Layout design experience is a plus Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race ...
Senior SoC Physical Design & Verification Engineer
Beaverton, OR · On-site
$143K - $147K/yr
Layout design experience is a plus Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race ...
Analog Engineer
$141K - $269K/yr
... and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities. - Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful ...
Analog Engineer
$141K - $269K/yr
... and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities. - Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful ...
Analog Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
... and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities. - Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful ...
Analog Engineer
Hillsboro, OR · On-site
$141K - $269K/yr
... and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities. - Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful ...
Layout design background is a plus Working knowledge of Extraction and STA methodology and tools Working knowledge of Computer Architecture Ability to work well in a team, being an excellent problem ...
Layout design background is a plus Working knowledge of Extraction and STA methodology and tools Working knowledge of Computer Architecture Ability to work well in a team, being an excellent problem ...
Layout design background is a plus Working knowledge of Extraction and STA methodology and tools Working knowledge of Computer Architecture Ability to work well in a team, being an excellent problem ...
Layout design background is a plus Working knowledge of Extraction and STA methodology and tools Working knowledge of Computer Architecture Ability to work well in a team, being an excellent problem ...
Structural Design Engineer
Hillsboro, OR · On-site
Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... converged layout. This will also include, but not be limited to, meeting timing, performance ...
Structural Design Engineer
Hillsboro, OR · On-site
Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... converged layout. This will also include, but not be limited to, meeting timing, performance ...
Job Title: Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is ... converged layout. This will also include, but not be limited to, meeting timing, performance ...
Job Title: Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is ... converged layout. This will also include, but not be limited to, meeting timing, performance ...
Construction Layout Technician
Lake Oswego, OR · On-site
$19 - $26/hr
The Construction Layout Technician is responsible for performing construction layout, verifying ... Review, interpret, and apply construction drawings, design documents, and as-built records.
Construction Layout Technician
Lake Oswego, OR · On-site
$19 - $26/hr
The Construction Layout Technician is responsible for performing construction layout, verifying ... Review, interpret, and apply construction drawings, design documents, and as-built records.
Physical Verification Engineer
Hillsboro, OR · On-site
$148K/yr
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue ...
Physical Verification Engineer
Hillsboro, OR · On-site
$148K/yr
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue ...
Hardware Design Engineer
Beaverton, OR · On-site
Support PCB layout activities by working with senior engineers to define component placement, routing requirements, and design constraints. * Participate in board bring-up, debugging, and validation ...
Hardware Design Engineer
Beaverton, OR · On-site
Support PCB layout activities by working with senior engineers to define component placement, routing requirements, and design constraints. * Participate in board bring-up, debugging, and validation ...
Hardware Engineer
Beaverton, OR · On-site
$130K - $172K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Hardware Engineer
Beaverton, OR · On-site
$130K - $172K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Hardware Engineer
Beaverton, OR · On-site
$128K - $169K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Hardware Engineer
Beaverton, OR · On-site
$128K - $169K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality. * Anticipate hardware bring-up ...
Hardware Engineer - Host Processor Systems
Beaverton, OR · On-site
$130K - $172K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality.Anticipate hardware bring-up ...
Hardware Engineer - Host Processor Systems
Beaverton, OR · On-site
$130K - $172K/yr
Use schematic capture, PCB layout, design rule checks (DRC), signal integrity analysis, and power integrity analysis to reduce project risk and improve design quality.Anticipate hardware bring-up ...
Semiconductor Device Modeling Engineer
Hillsboro, OR · On-site
$149K - $284K/yr
Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation. * The ability to work independently after the initial ramp-up time. Preferred ...
Semiconductor Device Modeling Engineer
Hillsboro, OR · On-site
$149K - $284K/yr
Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation. * The ability to work independently after the initial ramp-up time. Preferred ...
Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power Management Cells. Knowledge of circuit ...
Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power Management Cells. Knowledge of circuit ...
Hardware Design Engineer
Beaverton, OR · On-site
Support PCB layout activities by working with senior engineers to define component placement, routing requirements, and design constraints. * Participate in board bring-up, debugging, and validation ...
Hardware Design Engineer
Beaverton, OR · On-site
Support PCB layout activities by working with senior engineers to define component placement, routing requirements, and design constraints. * Participate in board bring-up, debugging, and validation ...
Experienced Analog/Mixed Signal IC Design Engineer
Hillsboro, OR · On-site
$220K/yr
The candidate must be able to architect, design, layout, measure and productize SiGe and silicon-based ICs and be comfortable with frequencies above 30GHz. Responsibilities: * Take an IC from concept ...
Experienced Analog/Mixed Signal IC Design Engineer
Hillsboro, OR · On-site
$220K/yr
The candidate must be able to architect, design, layout, measure and productize SiGe and silicon-based ICs and be comfortable with frequencies above 30GHz. Responsibilities: * Take an IC from concept ...
Layout Design information
See Oregon salary details
$17.75 is the 25th percentile. Wages below this are outliers.
$10.67 - $19.41
31% of jobs
$19.41 - $28.14
16% of jobs
The median wage is $30.76 / hr.
$28.14 - $36.88
11% of jobs
$36.88 - $45.61
15% of jobs
$51.07 is the 75th percentile. Wages above this are outliers.
$45.61 - $54.34
4% of jobs
$54.34 - $63.08
6% of jobs
$63.08 - $71.81
5% of jobs
$71.81 - $80.54
3% of jobs
$80.54 - $89.28
2% of jobs
$89.28 - $98.01
3% of jobs
$98.01 - $106.74
3% of jobs
$10
$43
$106
How much do layout design jobs pay per hour?
What is layout design?
What are the key skills and qualifications needed to thrive as a layout designer, and why are they important?
What are some common challenges faced by layout designers when collaborating with writers and marketers on a project?
What is the difference between Layout Design vs Graphic Design?
| Aspect | Layout Design | Graphic Design |
|---|---|---|
| Primary Focus | Arranging visual elements within a space or page | Creating visual content to communicate messages |
| Skills & Tools | Knowledge of typography, grid systems, software like Adobe InDesign | Creativity, color theory, software like Adobe Photoshop and Illustrator |
| Work Environment | Publishing, print media, web design | Advertising, branding, digital media |
| Credentials | Design degrees, certifications in layout or publishing | Design degrees, portfolio showcasing visual work |
While both roles involve visual creativity, Layout Design primarily focuses on organizing visual elements within a page or space to ensure clarity and flow, often in publishing or web design. Graphic Design, on the other hand, emphasizes creating compelling visual content to communicate messages across various media. Understanding these differences helps in choosing the right career path or job focus.
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Memory Circuit Design Engineer
Hillsboro, OR • On-site
Full-time
Medical, Retirement, PTO
Re-posted 4 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
Job description
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Qualifications:
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968