Layout Design Jobs in Oregon (NOW HIRING)

## Analog EngineerApplylocations: US, Oregon, Hillsboro: US, California, Santa Clara: US, Texas, Austin: US, Arizona, Phoenixtime type: Full timeposted on: Posted Todayjob requisition id: JR0284656# **Job Details:**## Job Description:**The Role and Impact** Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the Design Technology Platform (DTP), a team that is pivotal in shaping the future of analog and mixed-signal IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing cutting-edge analog circuits in advanced process nodes. Your work will directly impact Intel's ability to deliver the best-in-class foundational IP and product designs that drive innovation across client, server, and networking technologies. Collaborating with cross-functional teams, you will play a critical role in optimizing performance, power, area, and yield of circuits while pushing the boundaries of what is possible in semiconductor technology. **Key Responsibilities*** Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.* Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.* Create and validate floorplans, extract chip parameters, and simulate analog behavior models to ensure robust designs.* Develop test plans for design verification and evaluate test results to meet specification requirements.* Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.* Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful silicon implementation.* Analyze and resolve performance and circuit-related issues during design and post-silicon validation phases.* Serve as a technical interface to process technology, IP engineers, and product teams, leveraging design insights to influence future process node development.## **Qualifications:**You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.**Minimum Qualifications*** Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 8+ years of experience in analog and mixed-signal circuit design; or Master's degree with 6+ years of experience; or PhD with 4+ years of experience.3+ years of experience with the following technical skills* Expertise in analog circuit design, simulation, and verification.* Proficiency in CMOS technologies and layout understanding for analog circuits.* Experience with tape-out processes for analog mixed-signal circuits, including ADCs and DACs.* Knowledge of SoC analog layout design checks and methodologies.**Preferred Qualifications*** Advanced knowledge of high-speed parallel or serial I/O links, clock distribution, or voltage regulator design.* Experience with PLLs, bandgap references, inductors, transmission lines, and RF or millimeter-wave circuits.* Strong understanding of power delivery networks (PDN) and integrated power regulators.* Proven ability to collaborate across teams and influence decisions related to process technology and product development.Come be a part of Intel's mission to shape the future of technology. Apply today to join a team where innovation, collaboration, and excellence drive the creation of transformative products.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Oregon, Hillsboro## Additional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin## Business group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr