OR · On-site +1
... in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA ... Minimum of 5+ years proven experience in Mask and Layout Design. * Deep understanding of layout ...
OR · On-site +1
... in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA ... Minimum of 5+ years proven experience in Mask and Layout Design. * Deep understanding of layout ...
Beaverton, OR · On-site
$210K/yr
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
Beaverton, OR · On-site
$210K/yr
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
Beaverton, OR · On-site
$150 - $200/hr
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
Beaverton, OR · On-site
$150 - $200/hr
You will also drive mask design to implement layout view of designs. You will coordinate with IP consumers, help define production/bench-level test plans, and conduct design reviews of blocks with ...
Beaverton, OR · On-site
$210K/yr
You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex ...
Beaverton, OR · On-site
$210K/yr
You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex ...
You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex ...
You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex ...
Experience in scribe line layout design and process monitoring structure development. * Proficiency ... Knowledge of mask generation including Boolean/OPC . Job Type:Experienced Hire Shift:Shift 1 ...
Experience in scribe line layout design and process monitoring structure development. * Proficiency ... Knowledge of mask generation including Boolean/OPC . Job Type:Experienced Hire Shift:Shift 1 ...
$17.75 is the 25th percentile. Wages below this are outliers.
$10.67 - $19.41
31% of jobs
$19.41 - $28.14
16% of jobs
The median wage is $30.76 / hr.
$28.14 - $36.88
11% of jobs
$36.88 - $45.61
15% of jobs
$51.07 is the 75th percentile. Wages above this are outliers.
$45.61 - $54.34
4% of jobs
$54.34 - $63.08
6% of jobs
$63.08 - $71.81
5% of jobs
$71.81 - $80.54
3% of jobs
$80.54 - $89.28
2% of jobs
$89.28 - $98.01
3% of jobs
$98.01 - $106.74
3% of jobs
$10
$43
$106
| Aspect | Mask Layout Designer | IC Design Engineer |
|---|---|---|
| Primary Focus | Designing photomask layouts for semiconductor manufacturing | Designing integrated circuit architectures and circuit components |
| Skills & Certifications | Knowledge of mask design tools, semiconductor fabrication processes | Strong circuit theory, EDA tools, and semiconductor device knowledge |
| Work Environment | Semiconductor fabrication facilities, design labs | Design offices, R&D labs, semiconductor companies |
| Industry Usage | Used in photomask manufacturing for chip production | Used in chip and circuit development for various electronic devices |
While both roles are integral to semiconductor development, the Mask Layout Designer focuses on creating precise photomask patterns for manufacturing, whereas the IC Design Engineer develops the overall circuit architecture and logic. Understanding these distinctions helps professionals and employers align skills and expectations in the semiconductor industry.
For Mask Layout Designer jobs in Oregon, the most frequently searched job titles are:
The top searched job categories for Mask Layout Designer jobs in Oregon are:
Cities in Oregon with the most Mask Layout Designer job openings:
9.6
Based on 17 frontline employees who took The Breakroom Quiz
7th of 244 rated software companies
NVIDIA's GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions!
This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.
What you'll be doing:
You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
Performing physical layout for silicon interposer using Cadence tools.
Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
Propose layout design trade-offs to the PTL for resolution and implementation.
What we need to see:
Hold a B.S. Electrical Engineering or equivalent experience
Minimum of 5+ years proven experience in Mask and Layout Design.
Deep understanding of layout concepts in submicron CMOS technologies.
You are an authority with Cadence layout tools - particularly Virtuoso.
Knowledge of Integrity auto-routing is a plus.
Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
Proficient in scripting languages like Perl,Python, Skill, etc.
Should have knowledge of DRC and LVS checking flows, ability to customize decks.
Knowledge of APD package layout tool is a plus.
Good understanding of packaging technology is useful.
You can work optimally in a team, good interpersonal skills, passion and positive energy.
NVIDIA is widely considered to be one of the technology world's most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 258,750 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993
