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Junior Rtl Design Engineer Jobs in Wisconsin (NOW HIRING)

WI · On-site

$112K - $155K/yr

Summary Firefly is seeking an experienced FPGA RTL Design Engineer with 3+ years of direct professional Verilog hardware design experience. This role focuses on designing, implementing, verifying ...

Design Engineer Location: Darien, WI 53114 Hire Type: Direct Hire Compensation: $65,000-$78,000 ... Provide guidance and mentorship to junior engineers, designers, and technicians. * Create and ...

You will work across FPGA architecture, RTL development, verification, high-speed interfaces ... Develop reusable FPGA IP, design standards, and engineering best practices. * Evaluate emerging ...

WI · On-site

The engineer will handle full design responsibilities for quotes and orders, and provide general ... May provide guidance to drafters and junior design staff * Participates in product and process ...

Our mission is to be the global leader in design, engineering, and manufacturing solutions for the ... Experience mentoring junior engineers Why Work With MPE? * Medical, dental, vision, short- and ...

Transportation Design Engineer - CEIII

Middleton, WI · On-site

$77K - $95K/yr

Experience mentoring junior engineers and supporting project delivery from preliminary design through final plans and construction support. Additional Information At AECOM, we are committed to ...

Transportation Design Engineer - CEIII

Middleton, WI · On-site

$77K - $95K/yr

Experience mentoring junior engineers and supporting project delivery from preliminary design through final plans and construction support. Additional Information At AECOM, we are committed to ...

WI · On-site

$96K - $132K/yr

... technology co-design for future compute systems. We work in close collaboration with other ... QEMU, gem5, RTL, FGPA. * Contribute to performance and functional validation across abstraction ...

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Junior Rtl Design Engineer information

See Wisconsin salary details

$33.8K

$72.5K

$110.5K

How much do junior rtl design engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for junior rtl design engineer in Wisconsin is $72,471.00, according to ZipRecruiter salary data. Most workers in this role earn between $49,000.00 and $80,700.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Wisconsin?

For Junior Rtl Design Engineer jobs in Wisconsin, the most frequently searched job titles are:

What job categories do people searching Junior Rtl Design Engineer jobs in Wisconsin look for?

The top searched job categories for Junior Rtl Design Engineer jobs in Wisconsin are:

What cities in Wisconsin are hiring for Junior Rtl Design Engineer jobs?

Cities in Wisconsin with the most Junior Rtl Design Engineer job openings:

Infographic showing various Junior Rtl Design Engineer job openings in Wisconsin as of June 2026, with employment types broken down into 67% Full Time, 8% Part Time, and 25% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $72,471 per year, or $34.8 per hour.

FPGA Design Engineer III

WI • On-site

$112K - $155K/yr

Other

Medical, Dental, Vision, PTO

Posted 11 days ago


Key responsibilities

  • Design, develop, and verify FPGA logic using VHDL, Verilog, or SystemVerilog for Microchip PolarFire SoCs.

  • Create and optimize IP cores and custom peripherals/accelerators tailored to PolarFire's architecture.

  • Build RTL verification environments with testbenches using UVM methodologies for design correctness and coverage.


Firefly Aerospace rating

6.9

Company rating: 6.9 out of 10

Based on 11 frontline employees who took The Breakroom Quiz


Job description

Firefly Aerospace is a space and defense technology company on a mission to reliably and repeatedly launch, land, and operate space systems from Earth to the Moon and beyond. Headquartered in North Austin, Texas, Firefly looks for passionate and hardworking innovators to join our team and help fuel our successful trajectory into space.

Summary

Firefly is seeking an experienced FPGA RTL Design Engineer with 3+ years of direct professional Verilog hardware design experience. This role focuses on designing, implementing, verifying, and optimizing custom digital logic in the FPGA fabric of Microchip PolarFire SoCs for high‑reliability embedded systems.

Responsibilities
  • Design, develop, and verify FPGA logic using VHDL, Verilog, or SystemVerilog for Microchip PolarFire SoCs, including programmable logic, DSP blocks, and high‑speed interfaces such as PCIe, Ethernet, and SERDES.
  • Create and optimize IP cores and custom peripherals/accelerators tailored to PolarFire's architecture.
  • Integrate FPGA firmware with embedded processors (e.g., RISC‑V cores) and collaborate with software teams to support Board Support Packages (BSPs) and Linux kernel drivers.
  • Build RTL verification environments with testbenches using UVM methodologies for design correctness and coverage.
  • Perform functional verification, simulation, regression testing, and coverage analysis (e.g., functional, code, assertion).
  • Conduct synthesis, place‑and‑route, timing analysis, and debugging using tools such as Libero SoC, logic analyzers, and oscilloscopes.
  • Implement radiation‑tolerant and fault‑tolerant designs for space‑grade applications.
  • Develop automated test benches and CI pipelines for verification, including hardware‑in‑the‑loop testing.
  • Contribute to system architecture, security, and real‑time processing requirements.
  • Participate in code reviews, documentation, and stay updated on FPGA technologies and open‑source contributions.
Required Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3–5 years of professional RTL design experience using Verilog for FPGAs.
  • Demonstrated experience with the full FPGA design flow: RTL coding, simulation, synthesis, place‑and‑route, and static timing analysis.
  • Proficiency with at least one major FPGA tool suite (Xilinx Vivado or Intel Quartus).
  • Solid understanding of synchronous digital design, clock domain crossing, finite state machines, and resource/timing optimization.
Benefits

Firefly offers outstanding benefits for our employees, including generous health, dental, and vision plans with low deductibles, parental leave, educational reimbursement, short‑term disability, and flexible PTO options.

Compliance and Eligibility

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

Firefly Aerospace, Inc. is an Equal Opportunity Employer; employment with Firefly is governed based on merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability, or any other legally protected status.

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