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Cpu Rtl Design Engineer Jobs in Wisconsin (NOW HIRING)

PSRTEK

FPGA Engineer at Waukesha, WI

Waukesha, WI · On-site

$130K - $167K/yr

Architecture & Development (VHDL Focused) Own FPGA RTL design using VHDL as the primary HDL ... IEC 62304 for programmable logic. * Address safety (IEC 60601 1), EMC (IEC 60601 1 2), ...

Actalent

Senior Electrical Engineer

Waukesha, WI · On-site +1

$75 - $90/hr

Electrical Engineer - High-Speed Embedded Hardware Design We are seeking a highly skilled ... Modify and optimize existing CPU-based reference designs for custom embedded applications. * Design ...

EndoSec LLC

FPGA Engineer

Madison, WI

$131K - $168K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

LRS

Software Engineer, Intern

Waukesha, WI · On-site

$23.50/hr

You'll contribute to algorithm development and highperformance computing (GPU/CPU) on Linux, with a ... Familiarity with objectoriented programming and common design patterns. Analytical and ...

EndoSec LLC

FPGA Engineer

Madison, WI · On-site

$131K - $168K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Foxconn WI

Reliability Engineer

Mount Pleasant, WI · On-site

$99K - $124K/yr

Design and execute ORT plans for new and existing server and storage platforms, covering thermal ... Strong understanding of server architecture (CPU, memory, power supplies, I/O, fans, storage)

ConfigUSA

CUDA Programmer

Waukesha, WI · On-site

Waukesha, WI We are seeking a skilled CUDA Programmer to design, develop, and optimize high ... Work with CPU-GPU parallel programming models and optimize data transfer. * Leverage NVIDIA ...

Foxconn WI

Reliability Engineer

Mount Pleasant, WI

Design and execute ORT plans for new and existing server and storage platforms, covering thermal ... Strong understanding of server architecture (CPU, memory, power supplies, I/O, fans, storage)

Foxconn WI

Reliability Engineer

Mount Pleasant, WI · On-site

$99K - $124K/yr

Design and execute ORT plans for new and existing server and storage platforms, covering thermal ... Strong understanding of server architecture (CPU, memory, power supplies, I/O, fans, storage)

GE HealthCare

Software Engineer

Waukesha, WI · On-site

... CPU) * Minimize software errors by applying right software engineering principles and design thinking * Chase image quality and performance problems that cross algorithm, hardware, and system ...

Gehc

Software Engineer

Waukesha, WI · On-site

... CPU) * Minimize software errors by applying right software engineering principles and design thinking * Chase image quality and performance problems that cross algorithm, hardware, and system ...

Agile Enterprise Solutions

C/C++ Programmer

Waukesha, WI · On-site

... system design team and algorithm designers, utilizing the latest high-performance computing ... A CT image reconstruction engineer will be a part of a team working on implementing a revolutionary ...

Foxconn WI

Reliability Manager

Mount Pleasant, WI · On-site

GL6 Test & Reliability Engineering Employment Type: Full Time Location: SMC Reporting To: Aaron ... Design and implement ORT plans for new and existing server and storage platforms, covering thermal ...

Foxconn WI

Reliability Manager

Mount Pleasant, WI

Design and implement ORT plans for new and existing server and storage platforms, covering thermal ... Provide leadership, training, and support to engineers and technicians performing ORT activities.

All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Wisconsin

Cpu Rtl Design Engineer information

See Wisconsin salary details

$40.9K

$89K

$160K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 1, 2026, the average yearly pay for cpu rtl design engineer in Wisconsin is $88,974.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,600.00 and $99,400.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Wisconsin?

For Cpu Rtl Design Engineer jobs in Wisconsin, the most frequently searched job titles are:

What job categories do people searching Cpu Rtl Design Engineer jobs in Wisconsin look for?

The top searched job categories for Cpu Rtl Design Engineer jobs in Wisconsin are:

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Wisconsin as of August 2026, with employment types broken down into 80% Full Time, 5% Part Time, and 15% Contract. Highlights an 94% In-person, 2% Hybrid, and 4% Remote job distribution, with an average salary of $88,974 per year, or $42.8 per hour.

ASIC/FPGA Senior Verification Engineer - Milwaukee, WI or Mayfield Heights, OH

Milwaukee, WI • On-site

Info-Ways
IT Services • 51 - 200 employees
Learn more about Info-Waysexternal

$121K - $167K/yr

Contractor

Re-posted 2 days ago

Job description

Company Description

IT

Job Description

Role: ASIC/FPGA Senior Verification Engineer
Location: Milwaukee, WI or Mayfield Heights, OH
Duration: 6+ Months
BGV will be done for the selected candidates.
SCOPE: Individual Contributor - Responsible for participating in ASIC and FPGA implementation and verification for the Design Services organization
JOB SUMMARY:
The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.
The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog's Universal Verification Methodology (UVM) is preferred.
ESSENTIAL FUNCTIONS:
Basic understanding of CMOS ASIC fundamentals
Knowledge of all phases of ASIC design and test methodology
Basic understanding of Timing Analysis
Verilog / VHDL
Linux/Unix environment
Team Player
Good Communication Skills
Desired Capabilities
Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
Knowledge of System Verilog
Knowledge of UVM
FPGA based designs
Test Planning & Verification
EXPERIENCE AND EDUCATION:
A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
Minimum of 5 years' experience with standard cell ASIC and / FPGA design.
Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.
Demonstrated ability designing independently for medium/high complexity problems.
Strong oral and written communication skills in English and ability to present technical information.
Please respond with your word resume and requested details:
Full Name :
Work Authorization:
Contact Number :
Email ID :
Skype ID:
Current location:
Willing to relocate :
Rate/hr :

Additional Information

All your information will be kept confidential according to EEO guidelines.

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About Infoways

Sourced by ZipRecruiter

Whatever your ultimate Infor Platform destination, Infoways is vested in delivering support services that are scalable, and flexible, to your organization’s specific requirements. We create client centric teams that replicate your methodology and processes supported by our network of over 40,000 resources we deliver to meet your organization's requirements. Our tailored Service,Support scenarios include Customizations, Integration, implantation, migrations, and testing, across multiple GEOs.

Industry

It services and software development

Company size

51 - 200 Employees

Headquarters location

Langhorne, PA, US

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