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Junior Ic Layout Design Engineer Jobs (NOW HIRING)

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$114K - $220K/yr

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$114K - $220K/yr

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

Micron Technology

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

Effectively mentor junior team members * Contribute to the improvement of layout efficiency through ... IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$220K/yr

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

Micron

Staff Layout Designer

San Jose, CA

$72 - $122/hr

Effectively mentor junior team members * Contribute to the improvement of layout efficiency through ... IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience ...

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Junior Ic Layout Design Engineer information

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How much do junior ic layout design engineer jobs pay per year?

As of Jul 24, 2026, the average yearly pay for junior ic layout design engineer in the United States is $71,799.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,500.00 and $80,000.00 per year, depending on experience, location, and employer.

What does a Junior IC Layout Design Engineer do?

A Junior IC Layout Design Engineer assists in the physical design of integrated circuits (ICs) by translating schematic diagrams into actual chip layouts using specialized CAD tools. Their responsibilities include placing and routing circuit components, ensuring adherence to design rules, verifying layouts for manufacturability, and collaborating with senior engineers to optimize performance and reliability. This entry-level position is essential for creating functional and efficient semiconductor chips used in various electronic devices.

What are some typical challenges faced by Junior IC Layout Design Engineers during their first year on the job?

Junior IC Layout Design Engineers often encounter challenges such as learning to interpret complex circuit schematics, applying foundry-specific design rules, and mastering specialized EDA tools like Cadence Virtuoso. Additionally, collaborating efficiently with circuit designers and verification teams can be demanding as new engineers adjust to fast-paced project timelines and the need for high accuracy. However, with mentorship and hands-on experience, most junior engineers quickly build confidence and develop effective problem-solving skills.

What are the key skills and qualifications needed to thrive as a Junior IC Layout Design Engineer, and why are they important?

To thrive as a Junior IC Layout Design Engineer, a solid understanding of semiconductor physics, electronic circuits, and a relevant engineering degree are essential. Familiarity with EDA tools such as Cadence Virtuoso or Synopsys, and knowledge of design rule checking (DRC) and layout versus schematic (LVS) verification, are typically required. Attention to detail, problem-solving skills, and effective teamwork are important soft skills that help ensure high-quality layouts and collaboration with design teams. These competencies are crucial for producing reliable integrated circuit layouts that meet performance, manufacturability, and project deadlines.
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Junior Ic Layout Design Engineer jobs near you
Infographic showing various Junior Ic Layout Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $71,799 per year, or $34.5 per hour.
Staff Analog IC Layout Engineer

Staff Analog IC Layout Engineer

Elevate Semiconductor

San Diego, CA • On-site

$120K - $180K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 27 days ago

Job description

Elevate Semiconductor is at the forefront of shaping the future of semiconductor technology, driving innovation to enable the next generation of testing. We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to-market and enhanced capabilities. Our diverse product portfolio includes standard, semi-custom, and custom SKUs, all engineered for longevity and compatibility across evolving technological advancements. By focusing on low-power, high-density designs, we aim to lower the cost of testing while exceeding expectations on every project.

Join us in advancing the cutting edge of semiconductor innovation!

The Position

We are seeking a highly skilled Staff Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout and verification of highly complex, high-voltage, and mixed-signal solutions using advanced process technologies, ranging from 65nm CMOS to 100+V BCD. You will collaborate with a cross-functional team to optimize silicon design, leveraging mentorship and support from senior engineers to deliver innovative and cost-effective solutions.

Must be able to work onsite in San Diego,CA.

Responsibilities

  • Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level
  • Conducting floorplanning and placement of circuit components to optimize area, performance, and power
  • Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
  • Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy
  • Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance
  • Troubleshooting and resolving issues related to layout verification and manufacturing

Requirements

  • Bachelor’s degree in Electrical Engineering or a related field
  • Minimum of 8 years of professional experience in analog and mixed-signal IC layout design
  • Strong knowledge of analog CMOS circuits and device physics fundamentals
  • Solid understanding of the IC design, qualification, and manufacturing lifecycle
  • Hands-on experience with industry-standard EDA tools for analog and mixed-signal design (e.g., Cadence, Mentor Graphics, Tanner)
  • Proficiency in performing LVS and DRC verification using Cadence or Mentor tools

Preferences

  • Layout experience with STI High voltage (100V+) BCD and LDMOS processes
  • Layout experience with mixed voltage (multiple supply rails, 6 or more) domains
  • Layout experience with high speed multi Gbps circuits.
  • Layout experience in ultra-high accuracy and precision circuits.
  • Layout experience with high resolution data converters.
  • Layout experience with BiCMOS process technology.
  • Programming and scripting ability a strong plus, particularly in SKILL and Calibre scripts

Why Join Us?

At Elevate Semiconductor, you’ll be part of a dynamic team working on innovative technologies that shape the future of the semiconductor industry. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth in a collaborative environment.

Apply Today!

If you are passionate about digital design and eager to contribute to groundbreaking semiconductor solutions, we want to hear from you!

Benefits

  • 100% Employer Paid Health Insurance (Medical, Dental, Vision)
  • Unlimited Paid Time Off
  • Performance Bonuses
  • Free Lunch Catered in by Local Restaurants
  • Private Equity Options
  • Retirement Plans
  • Sabbatical Program
  • Tuition Reimbursement
  • Volunteer Days
  • Relocation Assistance
  • Conference Attendance Support
  • Biweekly Phone Stipend
  • Employee Assistance Program

The salary range for this role is $120,000-$180,000.00.

Please note: While a salary range is provided, the final compensation will depend on your experience, skill set, and how well you're able to highlight your background throughout the interview process.