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Part Time Ic Layout Design Engineer Jobs (NOW HIRING)

... Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura ... This position is a part time role with up to 24hrs a week. Clearance Level: An ACTIVE clearance is ...

... Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura ... This position is a part time role with up to 24hrs a week. Clearance Level: An ACTIVE clearance is ...

Design layout of RF/Microwave, power, microprocessor, high-speed interface, and mixed-signal Printed Circuit Boards for satellite applications in concert with the electrical design engineers

Design layout of RF/Microwave, power, microprocessor, high-speed interface, and mixed-signal Printed Circuit Boards for satellite applications in concert with the electrical design engineers

Product Design Engineer

Pomona, CA Β· On-site

$18 - $21/hr

Manage new tooling programs including mold layout and detail design. * Work with DFM process given ... Provide Engineering support to Production on existing tooling problems. * Review mold issues with ...

Product Design Engineer

Pomona, CA Β· On-site

$18 - $21/hr

Manage new tooling programs including mold layout and detail design. * Work with DFM process given ... Provide Engineering support to Production on existing tooling problems. * Review mold issues with ...

Utilize computer-aided engineering and design tools (e.g., Altium, OrCAD, etc.) for circuit design and layout. * Create and maintain design documentation, drawings, and engineering change orders.

Design Engineer - Municipal

Willmar, MN Β· On-site

$58K - $90K/yr

Perform basic design computations, preliminary layout and design, research and prepare rough drafts ... a full-time basis, part-time basis or internship for any employer without restriction. Bolton ...

Design Engineer - Municipal

Oakdale, MN Β· On-site

$58K - $90K/yr

Perform basic design computations, preliminary layout and design, research and prepare rough drafts ... a full-time basis, part-time basis or internship for any employer without restriction. Bolton ...

Design Engineer - Municipal

Baxter, MN Β· On-site

$58K - $90K/yr

Perform basic design computations, preliminary layout and design, research and prepare rough drafts ... part-time basis, or internship for any employer without restrictions. Bolton & Menk does not ...

Design Engineer - Municipal

Fairmont, MN Β· On-site

$58K - $90K/yr

Perform basic design computations, preliminary layout and design, research and prepare rough drafts ... a full-time basis, part-time basis or internship for any employer without restriction. Bolton ...

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Part Time Ic Layout Design Engineer information

See salary details

$45K

$120.8K

$185.5K

How much do part time ic layout design engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for part time ic layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What is a part time IC layout design engineer?

Part Time IC Layout Design Engineers are professionals who work on the physical design and layout of integrated circuits (ICs), typically on a part-time basis. They use specialized software to arrange electronic components and wiring on a semiconductor chip to meet design specifications for performance, size, and power consumption. These engineers collaborate with circuit designers and verification teams to ensure the layout is manufacturable and meets all technical requirements. Working part-time allows them flexibility while still contributing to important aspects of chip design projects.

What are the key skills and qualifications needed to thrive as a part time IC layout design engineer?

To thrive as a Part Time IC Layout Design Engineer, you need a strong background in electrical engineering principles, semiconductor device physics, and experience with IC layout design, typically supported by a relevant degree. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, and knowledge of industry design rules are essential. Attention to detail, problem-solving abilities, and effective communication are valuable soft skills in this role. These competencies ensure accurate, efficient layout designs that meet performance, manufacturability, and reliability standards in the semiconductor industry.

What are some common challenges faced by part time IC layout design engineers, and how can they be managed effectively?

Part-time IC Layout Design Engineers often face challenges related to time management and staying aligned with project timelines, especially when collaborating with full-time team members. Communication is keyβ€”regular check-ins and clear documentation help ensure that design changes and project updates are well understood. Additionally, because IC layout work often requires precision and adherence to strict design rules, part-time engineers must be diligent in maintaining quality standards while balancing multiple priorities. Leveraging version control tools and participating in team meetings, even remotely, can help manage these challenges effectively.

What is the difference between Part Time Ic Layout Design Engineer vs Full Time Ic Layout Design Engineer?

AspectPart Time Ic Layout Design EngineerFull Time Ic Layout Design Engineer
Work HoursFewer hours, typically less than 30 hours/weekStandard full-time hours, usually 40 hours/week
CredentialsSimilar certifications, such as EE degree or equivalentSame as part-time, often with more experience
Work EnvironmentFlexible, often remote or contract-basedOn-site or full-time office setting
Industry UsageCommon in consulting, freelance, or project-based rolesStandard employment in semiconductor companies or design firms

In summary, a Part Time Ic Layout Design Engineer works fewer hours with flexible arrangements, often on a contract basis, while a Full Time Ic Layout Design Engineer maintains standard hours and is typically a permanent employee. Both roles require similar skills and credentials but differ mainly in work hours and employment type.

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Infographic showing various Part Time Ic Layout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Circuit Design Engineer

Lexington, MA β€’ Hybrid

Full-time

Retirement, PTO

Posted 5 days ago


Job description

Circuit Design Engineer

Clearance Level: Must have an Active Secret Clearance to be considered for this opportunity due to the nature of the work. Must be US Citizen 

Location: This role is 100% remote - must be willing to travel up to 3 times a year.

At Aquila Technology, you will see our team's passion every day, whether we are building a robust, policy-compliant IT system or stress-testing a system to identify gaps and security vulnerabilities. To own the advantage, we ensure our team owns results and gets the work done right the first time by deploying smart, purposeful solutions that work. Aquila is the right people with the right skills driving the right outcomes. We call this the Aquila Advantage.

About the Role:

Aquila Technology is seeking a Circuit Design Engineer to support one of the nation's premier defense research organizations. The team develops custom digital & mixed-signal Readout Integrated Circuits (ROICs) for advanced imager applications. An analog/mixed-signal layout design engineer is needed for implementation of imager circuit building blocks.

Must Have

  • Clearance Level: Currently holds a Secret Clearance (OR a higher clearance)
  • 10 years - Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura
  • 10 years - Experience in top level floor planning as well as block level design
  • 10 years - Experience with multiple design tape outs
  • 10 years - Deep-submicron CMOS Layout (12nm - 22nm, Global Foundries)
  • Presentation, verbal and written communication skills
  • Strong team communication
  • Strong Verbal and Written Communication

Responsibilities include but are not limited to:

  • Physical layout and verification of integrated circuit building blocks
  • Full-chip assembly and top-level verification.
  • Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.
Must Have:
  • Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz
  • Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.
  • Proven track record of multiple design tape outs
  • Extensive experience in top level floor planning as well as block level design
  • Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.

Benefits and Perks:
Aquila team members experience the opportunity to be part of a fast-paced, customer-focused, and technically innovative work environment. Aquila strives to deliver the best of the best in technical services to our customers. Candidates that possess a love for technical challenges, a desire to constantly learn, and the desire to establish themselves as critical players within a team will enjoy calling Aquila Technology home.
Our Perks Include:
PTO - 15 days (vacation/sick) 10 paid holidays - 6 standard (New Year's, Memorial Day, Independence Day, Labor Day, Thanksgiving, and Christmas) - 4 floating holidays prorated based on your day of hire:

  • 1.5 paid days, or 12 hours, for approved volunteer work
  • 1 week of paid maternity/paternity LOA after 1 year of Full-time employment

Tuition & Training Reimbursement- 5K annually for pre-approved, Eligible full-time team members who have completed a minimum ofsix (6) months of employment may apply for tuition reimbursement for approved, job-related courses taken through an accredited college or university. Team members must achieve a grade of “B” or better to qualify for reimbursement.Aquila will reimburse up to $5,000 per fiscal year for tuition expenses only. Expenses related to training programs, certifications, books, materials, meals, transportation, or other non-tuition costs are not eligible under the Tuition Reimbursement Program. All tuition reimbursement requests must be submitted to and approved by the team member's Manager prior to course registration. Reimbursement will be issued upon successful course completion and submission of final grades and proof of payment.

401K with Fidelity - Eligible to participate following 90 days of employment. Company match on employee contribution:

  • $1/$1 up to 3%, then .50 cents / $1 for 4th and 5th %s
  • Fully vested from day one
  • Company match does not apply to catch-up contribution

Cell Phone & Internet Reimbursed up to $150 monthly to cover cell phone, data, and home internet expenses. Aquila Technology will reimburse team members who work from home ONLY for cell phone/mobile device fees for work-related communications and/or operations each month. Employees eligible for this benefit must work remote 2 days a week or more to qualify.

Buy Your Own Device (BYOD) - Team members are eligible for reimbursement of up to $1,500 every three (3) years for the purchase of electronic equipment used to access corporate services. To qualify for this benefit, employees must have completed a minimum of six (6) months of employment and must agree to and sign the Device Minimum Configuration Form prior to reimbursement. Electronic devices eligible under the Buy Your Own Device (BYOD) program are limited to cell phones, laptops, and tablets.

Work Location: Work from Home: This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.
Core Work Hours: This position is a part time role with up to 24hrs a week.
Clearance Level: An ACTIVE clearance is required for this role. Do not submit candidates who do not meet this requirement.
Interview Process: 1st round will be a Zoom with the hiring manager. 2nd round will be a Zoom with additional team members as needed.

We are an Equal Opportunity Employer