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Junior Ic Layout Design Engineer Jobs in Missouri

Axion Recruitment

Mechanical Design Engineer

Kansas City, MO · On-site

$74K - $100K/yr

Mechanical Design Engineer * Kansas City, MO - Relocation on offer * $110,000 - $140,000 * Monday ... Mentor junior engineers and review engineering drawings * Drive continuous improvement and ...

Liberty

Engineer, Line Design

Joplin, MO · On-site

Junior level engineer: With some guidance, will prepare models, perform route selection, assist ... general layout drawings. Plan and coordinate work for engineering techs, drafting techs, and ...

Amphenol

Design Engineer

Springfield, MO · On-site

$90K - $100K/yr

Ability to mentor junior staff and collaborate across disciplines. * Ability to apply deductive reasoning to evaluate engineering tradeoffs. POSITRONIC RESERVES THE RIGHT TO MODIFY, INTERPRET, OR ...

Positronic

Design Engineer

Springfield, MO · On-site

$85 - $110/hr

Ability to mentor junior staff and collaborate across disciplines. * Ability to apply deductive reasoning to evaluate engineering tradeoffs. POSITRONIC RESERVES THE RIGHT TO MODIFY, INTERPRET, OR ...

Posted today

Tri Alpha Energy Inc.

PCB Design Engineer

California, MO · On-site

$115 - $145/hr

We are applying science and engineering to design transformational technologies. Whether it ... The ideal candidate combines strong layout and schematic skills with hands‑on lab experience and ...

New

CivicMinds, Inc.

Design Engineer

Moberly, MO · On-site

... Engineering with other process and assembly problem solving. * Investigate, propose, and manage new ... Operate CAD system to layout and develop related products * Understanding of geometric dimensioning ...

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Junior Ic Layout Design Engineer information

What does a junior IC layout design engineer do?

A Junior IC Layout Design Engineer assists in the physical design of integrated circuits (ICs) by translating schematic diagrams into actual chip layouts using specialized CAD tools. Their responsibilities include placing and routing circuit components, ensuring adherence to design rules, verifying layouts for manufacturability, and collaborating with senior engineers to optimize performance and reliability. This entry-level position is essential for creating functional and efficient semiconductor chips used in various electronic devices.

What are some typical challenges faced by a junior IC layout design engineer during their first year on the job?

Junior IC Layout Design Engineers often encounter challenges such as learning to interpret complex circuit schematics, applying foundry-specific design rules, and mastering specialized EDA tools like Cadence Virtuoso. Additionally, collaborating efficiently with circuit designers and verification teams can be demanding as new engineers adjust to fast-paced project timelines and the need for high accuracy. However, with mentorship and hands-on experience, most junior engineers quickly build confidence and develop effective problem-solving skills.

What are the key skills and qualifications needed to thrive as a junior IC layout design engineer, and why are they important?

To thrive as a Junior IC Layout Design Engineer, a solid understanding of semiconductor physics, electronic circuits, and a relevant engineering degree are essential. Familiarity with EDA tools such as Cadence Virtuoso or Synopsys, and knowledge of design rule checking (DRC) and layout versus schematic (LVS) verification, are typically required. Attention to detail, problem-solving skills, and effective teamwork are important soft skills that help ensure high-quality layouts and collaboration with design teams. These competencies are crucial for producing reliable integrated circuit layouts that meet performance, manufacturability, and project deadlines.

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Junior Ic Layout Design Engineer jobs near you
Infographic showing various Junior Ic Layout Design Engineer job openings in Missouri as of June 2026, with employment types broken down into 81% Full Time, and 19% Part Time. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution.

Analog and Mixed Signal Design Engineer

Socket.dev

California, MO • On-site

$110 - $176/hr

Other

Medical, Dental, Vision, Retirement, PTO

Posted 5 days ago

Key responsibilities

  • Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.

  • Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.

  • Establish post-silicon testing guidelines and oversee the validation process by analyzing and reviewing test data.

Job description

Job Description Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Responsibilities
  • Circuit Design & Verification: Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
  • Layout & Post-Layout Validation: Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.
  • Digital Modeling: Build behavioral and gate-level models for IPs and validate functionality through Verilog simulations.
  • IP Delivery & Documentation: Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
  • Silicon Bring-up & Validation: Establish post-silicon testing guidelines and oversee the validation process by analyzing and reviewing test data.
Education & Experience
  • MS or PhD in Electrical Engineering
  • 6+ years of mixed-signal and analog design experience.
Design Expertise
  • Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
  • Strong understanding of layout effects on circuit performance.
  • Familiarity with Verilog modeling, digital circuits, and standard digital implementation flows.
EDA Tools
  • Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or PrimeSim.
  • Experience with Synopsys PrimeTime and Verilog simulators such as Xcelium or VCS.
Professional Attributes
  • Excellent communication and teamwork skills.
  • Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.
Desired Skills
  • Prior experience building and delivering mixed-signal IPs.
  • General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
  • Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
  • Familiarity with ESD (Electrostatic Discharge) and latch-up design rules.
  • Silicon Failure Analysis (FA) and debugging skills.
Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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