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Internship Serdes Design Engineer Jobs in Riverside, CA

Marvell

Senior Staff Emulation Engineer

Irvine, CA · On-site

  • Life

  • Retirement

What You Can Expect Build complex Subsystem emulation models, including design integration ... every stage - from internship to retirement and through life's most important moments. Our ...

Broadcom

ATE Test Development Engineer

Irvine, CA

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed serdes (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom, Inc.

ATE Test Development Engineer

Irvine, CA · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed serdes (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom

ATE Test Development Engineer

Irvine, CA

$108K - $192K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed serdes (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom, Inc.

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $192K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed serdes (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom

product application engineer

Irvine, CA · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Fundamentally your role is to help secure customer design wins and assist customers in bringing ... Hardware, high-speed SerDes, or system (board) experience is a plus. Experience with high-speed ...

New

Broadcom, Inc.

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $172K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

Broadcom

ATE Test Development Engineer

Irvine, CA · On-site

$108K - $172K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... Engineer. Products include networking switches for NIC, Scale Up, Scale Out, Scale Across ... speed SERDES (>100G) and bring the product from design to manufacturing. * Test Hardware ...

WSP

Associate Mechanical Engineer - Buildings

Riverside, CA · On-site

$79K - $109K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Associate Mechanical Engineer will support the planning, design, and delivery of mechanical ... Prior internship or co-op experience in consulting engineering or the built environment. * Exposure ...

WSP

Associate Mechanical Engineer - Buildings

Riverside, CA · On-site

$79K - $109K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Associate Mechanical Engineer will support the planning, design, and delivery of mechanical ... Prior internship or co-op experience in consulting engineering or the built environment. * Exposure ...

Marvell

Design Verification Engineer - Early Career

Irvine, CA · On-site

$146K - $178K/yr

  • Life

  • Retirement

... design meets our customers' specifications. As a new engineer at Marvell, we value your ideas, and ... every stage - from internship to retirement and through life's most important moments. Our ...

Danaher

Software Engineer Internships

Pomona, CA · On-site

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

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Internship Serdes Design Engineer information

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How much do internship serdes design engineer jobs pay per hour?

As of Aug 13, 2026, the average hourly pay for internship serdes design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an internship Serdes design engineer?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an internship Serdes design engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

What does an internship Serdes design engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.
What are popular job titles related to Internship Serdes Design Engineer jobs in Riverside, CA? For Internship Serdes Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
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What cities near Riverside, CA are hiring for Internship Serdes Design Engineer jobs? Cities near Riverside, CA with the most Internship Serdes Design Engineer job openings:
Internship Serdes Design Engineer jobs near you
Infographic showing various Internship Serdes Design Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 8% Part Time, and 6% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $42,048 per year, or $20.2 per hour.

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

Irvine, CA • On-site

$165K - $260K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 15 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

15th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
  • Develop, maintain, and optimize physical verification flows for advanced node SoC's.
  • Interpret and implement foundry Design Rule Manuals (DRM) - translate rule updates into verified flow changes
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
  • Perform ESD verification - validate protection strategies, current paths, and CDM/HBM compliance
  • Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
  • Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:
  • Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
  • Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
  • Deep expertise in DRC, LVS, PERC and ESD verification methodologies
  • Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
  • Direct foundry DRM experience - able to read, interpret, and implement complex rule decks
  • Experience at advanced nodes (4nm and below)
  • Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
  • Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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About SpaceX

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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