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Internship Serdes Design Engineer Jobs in Riverside, CA

Marvell

Digital Design Engineer

Irvine, CA

$146K/yr

  • Life

  • Retirement

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... every stage - from internship to retirement and through life's most important moments. Our ...

Rivian

Exterior Trim Mechanical Design Engineer

Irvine, CA · On-site

$85K - $94K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Bachelor's or Master's Degree in Mechanical Engineering ... Preferred: 1-2 examples of design internship experience or a similar professional role. * Technical ...

Rivian

Exterior Trim Mechanical Design Engineer

Irvine, CA · On-site

$85K - $94K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Bachelor's or Master's Degree in Mechanical Engineering ... Preferred: 1-2 examples of design internship experience or a similar professional role. * Technical ...

Marvell Technology, Inc.

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

  • Life

  • Retirement

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... every stage - from internship to retirement and through life's most important moments. Our ...

Rivian

Exterior Trim Mechanical Design Engineer

Irvine, CA · On-site

$85K - $94K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Preferred: 1-2 examples of design internship experience or a similar professional role. * Technical ... Bachelor's or Master's Degree in Mechanical Engineering. * Preferred: 1-2 examples of design ...

Marvell

Senior Staff Digital Design Engineer

Irvine, CA · On-site

  • Life

  • Retirement

Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you'll be a ... every stage - from internship to retirement and through life's most important moments. Our ...

Broadcom, Inc.

Analog & RF IC Senior Layout Engineer

Irvine, CA · On-site

$216K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Mission We are looking for a high-energy engineer to support our circuit design teams in ... SerDes, and PLLs). * Tool Proficiency: Deep familiarity with the Cadence Virtuoso tool suite for ...

Synaptics Incorporated

Hardware Engineer, ATE

Irvine, CA · On-site

$86 - $135.30/hr

Design, develop, and validate hardware for ATE systems * Translate test requirements into circuit ... Experience with high‑speed digital or RF test (e.g. >1 GHz, SerDes, high‑speed PHYs)

Broadcom

Analog & RF IC Senior Layout Engineer

Irvine, CA · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Mission We are looking for a high-energy engineer to support our circuit design teams in ... SerDes, and PLLs). * Tool Proficiency: Deep familiarity with the Cadence Virtuoso tool suite for ...

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Showing results 21-40

All JobsSerdes Design Engineer JobsInternship Serdes Design Engineer JobsInternship Serdes Design Engineer Jobs in Riverside, CA

Internship Serdes Design Engineer information

See Riverside, CA salary details

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How much do internship serdes design engineer jobs pay per hour?

As of Aug 13, 2026, the average hourly pay for internship serdes design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an internship Serdes design engineer?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an internship Serdes design engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

What does an internship Serdes design engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.
What are popular job titles related to Internship Serdes Design Engineer jobs in Riverside, CA? For Internship Serdes Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
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What cities near Riverside, CA are hiring for Internship Serdes Design Engineer jobs? Cities near Riverside, CA with the most Internship Serdes Design Engineer job openings:
Internship Serdes Design Engineer jobs near you
Infographic showing various Internship Serdes Design Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 8% Part Time, and 6% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $42,048 per year, or $20.2 per hour.

Digital Design Engineer

Marvell

Irvine, CA

$146K/yr

Full-time

Life, Retirement

Re-posted 18 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Connectivity Group

What You Can Expect

  • Responsible for design, verification, implementation (ASIC) for high-performance, physical layer, high speed wired data communication networks.
  • Develop ASIC specification, architecture, and micro-architecture of major functional blocks in complex SOC solutions
  • Development/simulation of RTL hardware implementations in Verilog and System Verilog
  • Document and Execute verification plan
  • Analyze and improve design functionality with Lint, CDC and Power analysis
  • Participate and contribute in reviews
  • Work and communicate effectively with global team

What We're Looking For

  • 1-3 years plus experience in developing, implementing, and testing high performance communications and DSP ASIC products
  • Experience mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications.
  • Must be familiar with signal processing circuit structure and architecture and high performance datapath DSP circuit design and optimization.
  • Must have extensive RTL experience including design, verification, and synthesis.
  • Must have strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows.
  • Must be familiar with reusable HDL coding styles and design for high volume manufacture
  • Experience in bit-exact MATLAB and C/C++ based system simulation and evaluation a plus.
  • Familiarity with DSP and PHY layer communication protocols of 802.3 is a plus.

Expected Base Pay Range (USD)

97,700 - 144,410, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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