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Internship Serdes Design Engineer Jobs in Riverside, CA

Celero Communications, Inc.

SerDes Lead Designer

Irvine, CA · On-site

$150K - $250K/yr

Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design * Proven record of taking high-speed SerDes design to tape-out and volume ...

Celero Communications, Inc.

SerDesLeadDesigner

Irvine, CA · On-site

$150K - $250K/yr

Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design * Proven record of taking high-speed SerDes design to tape-out and volume ...

Celero Communications, Inc.

PLLDesign Engineer

Irvine, CA · On-site

$150K - $250K/yr

... Design Engineer -who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC ...

Marvell

Staff Engineer, Analog IC Design

Irvine, CA · On-site

$216K/yr

... highly sophisticated CMOS transceiver/SERDES products. Responsibilities would include ... every stage - from internship to retirement and through life's most important moments. Our ...

Marvell

Staff Physical Design Engineer

Irvine, CA · On-site

$146K - $150K/yr

In this unique role, you'll have the opportunity to work on both the physical design and ... every stage - from internship to retirement and through life's most important moments. Our ...

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Internship Serdes Design Engineer information

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How much do internship serdes design engineer jobs pay per hour?

As of Jun 14, 2026, the average hourly pay for internship serdes design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship Serdes Design Engineer, and why are they important?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an Internship Serdes Design Engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

What does an Internship Serdes Design Engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.
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Internship Serdes Design Engineer jobs near you
Infographic showing various Internship Serdes Design Engineer job openings in Riverside, CA as of June 2026, with employment types broken down into 1% Internship, 1% As Needed, 97% Full Time, and 1% Temporary. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $42,048 per year, or $20.2 per hour.

SerDes Lead Designer

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Posted 8 days ago

Job description

About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI.
Preferred Location: Irvine, CA
Alternate Locations: San Jose, CA | Vancouver, BC Canada | Ottawa, ON, Canada
Candidate will have the opportunity to architect and design SerDes for next generation transceivers.
What You Will Do:
  • Define architecture, specifications, and circuit topologies for next-generation SerDes
  • Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
  • Design high-performance analog/mixed-signal circuits in advanced node technologies
  • Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
  • Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
  • Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
  • Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
  • Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
  • Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring:
  • Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
  • Proven record of taking high-speed SerDes design to tape-out and volume production
  • Experience in lab bring-up, characterization, and debugging designs that reach out production
  • Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
  • Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
  • Strong communication and documentation skills

Salary Range
$150,000 - $250,000 Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.

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