ZipRecruiter

Log In

1

Internship Serdes Design Engineer Jobs (NOW HIRING)

Celero Communications, Inc.

SerDes Lead Designer

Irvine, CA · On-site

$150K - $250K/yr

Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design * Proven record of taking high-speed SerDes design to tape-out and volume ...

Apple

SerDes Micro Architect

San Diego, CA · On-site

You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design ... You will work with signal integrity engineers to determine system requirements. BS degree in ...

Apple

SerDes Micro Architect

Cupertino, CA · On-site

You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design ... You will work with signal integrity engineers to determine system requirements. BS degree in ...

Apple

SerDes System Validation Engineer

Cupertino, CA · On-site

We are looking for a SerDes System Validation Engineer to lead system validation of mixed-signal ... In this highly visible role, you will actively work within Analog-Mixed/Signal design team and ...

Apple

SerDes Micro Architect

Beaverton, OR

You will work with silicon evaluation and design verification teams to define expected behavior ... You will work with signal integrity engineers to determine system requirements. Preferred ...

Apple

SerDes Micro Architect

Beaverton, OR · On-site

You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design ... You will work with signal integrity engineers to determine system requirements. BS degree in ...

next page

Showing results 1-20

People also search for

All JobsInternship Serdes Design Engineer Jobs

Internship Serdes Design Engineer information

See salary details

$9

$19

$36

How much do internship serdes design engineer jobs pay per hour?

As of Jun 8, 2026, the average hourly pay for internship serdes design engineer in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship Serdes Design Engineer, and why are they important?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an Internship Serdes Design Engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

What does an Internship Serdes Design Engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.
More about Internship Serdes Design Engineer jobs
What cities are hiring for Internship Serdes Design Engineer jobs? Cities with the most Internship Serdes Design Engineer job openings:
What are the most commonly searched types of Serdes Design Engineer jobs? The most popular types of Serdes Design Engineer jobs are:
What states have the most Internship Serdes Design Engineer jobs? States with the most job openings for Internship Serdes Design Engineer jobs include:
What job categories do people searching Internship Serdes Design Engineer jobs look for? The top searched job categories for Internship Serdes Design Engineer jobs are:
Internship Serdes Design Engineer jobs near you
Infographic showing various Internship Serdes Design Engineer job openings in the United States as of May 2026, with employment types broken down into 1% Internship, and 99% Full Time. Highlights an 87% Physical, 8% Hybrid, and 5% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.
Principal Analog Circuit Design Engineer - SerDes

Principal Analog Circuit Design Engineer - SerDes

Intel

Santa Clara, CA

$237K/yr

Full-time

Medical, Retirement, PTO

Posted 8 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

8th of 139 rated electronics manufacturers

Job description

Job Details:Job Description: 

We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.

This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential. As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.

The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.

Desired traits:

Excellent communication, documentation, and presentation skills.

Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.

Demonstrated leadership in cross-functional technical discussions and decision-making.

Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving

Qualifications:

Minimum Qualifications

Master's degree in Electrical Engineering, Electronics Engineering, or related field.

8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications. Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).

Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.

Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).

Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Preferred Qualifications

Ph.D. in Electrical Engineering, Electronics Engineering, or related field.

10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.

Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.

Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.

Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).

Strong understanding of signal integrity, channel modeling, and system-level link performance.

Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews..

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

View All Intel Jobs

Apply