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Internship Serdes Design Engineer Jobs in Colorado

Broadcom

Package Design Engineer

Fort Collins, CO

$141K - $226K/yr

These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You ... General flip-chip BGA package design & engineering * Project management and customer interface for ...

Broadcom

Package Design Engineer

Fort Collins, CO

$134K/yr

These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You ... General flip-chip BGA package design & engineering * Project management and customer interface for ...

CenCore LLC

Product Design Engineer I

Aurora, CO · On-site

$131K - $157K/yr

The Product Design Engineer I assists with design reviews, technical problem-solving, product ... Prior internship or professional experience in manufacturing, defense, aerospace, secure ...

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Internship Serdes Design Engineer information

What are the key skills and qualifications needed to thrive as an internship Serdes design engineer?

To thrive as an Internship Serdes Design Engineer, you need a solid background in electrical engineering principles, digital and analog circuit design, and familiarity with SerDes architectures, typically gained through coursework or related experience. Knowledge of simulation tools (such as Cadence, HSPICE, or MATLAB), and experience with hardware description languages like Verilog or VHDL are commonly expected. Strong problem-solving skills, attention to detail, and effective communication help interns excel in collaborative and fast-paced project environments. Mastery of these skills is crucial for supporting high-speed interface design, ensuring signal integrity, and contributing effectively to engineering teams.

What types of projects and responsibilities can I expect as an internship Serdes design engineer?

As an Internship Serdes Design Engineer, you can expect to work on tasks such as assisting in the design and simulation of high-speed serial interfaces, supporting validation and debugging efforts, and collaborating with senior engineers to optimize signal integrity. You may be involved in lab measurements, data analysis, and documentation of design processes. Interns typically participate in team meetings and contribute to the development of test benches or verification environments, providing a valuable opportunity to gain hands-on experience in both digital and analog design aspects within a collaborative engineering team.

What is the difference between Internship Serdes Design Engineer vs Serdes Design Engineer?

AspectInternship Serdes Design EngineerSerdes Design Engineer
QualificationsEnrolled in or recent graduate in Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering, with experience preferred
Work EnvironmentInternship program, collaborative team, learning-focusedFull-time professional role, project-driven, independent responsibilities
Industry UsageEntry-level, training, and development stageDesign, development, and testing of Serdes components in industry projects

The Internship Serdes Design Engineer role is an entry-level position aimed at students or recent graduates gaining hands-on experience. In contrast, a Serdes Design Engineer is a full-time professional responsible for designing and developing high-speed serial transceivers. The internship provides foundational exposure, while the full engineer role involves independent project execution and advanced design tasks.

What does an internship Serdes design engineer do?

An Internship Serdes (Serializer/Deserializer) Design Engineer assists in designing high-speed data transmission circuits that convert data between serial and parallel forms. They typically work under the guidance of experienced engineers to help develop, test, and optimize SerDes blocks used in integrated circuits for applications like networking, data centers, and consumer electronics. Tasks may include schematic design, simulation, layout, and validation of high-speed analog and mixed-signal circuits. The internship provides hands-on experience with industry-standard electronic design automation (EDA) tools and exposure to the full chip design flow.

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Cities in Colorado with the most Internship Serdes Design Engineer job openings:

Internship Serdes Design Engineer jobs near you

Package Design Engineer

Broadcom

Fort Collins, CO

$141K - $226K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 15 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

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Job Description:

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

RESPONSIBILITIES:

  • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
  • Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
  • Schedule, prioritize, & track your work across 2+ projects simultaneously
  • General flip-chip BGA package design & engineering
  • Project management and customer interface for your design projects
  • Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.
  • Physical design (layout) is a foundational responsibility in this role


EDUCATION/EXPERIENCE & REQUIREMENTS:

  • BSEE or similar field and 12+ years' experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 10+ years' work experience
  • Knowledge of package-level signal integrity and power integrity, to apply to package designs
  • Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
  • Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
  • Self-management and organization skills
  • Preferred candidates will also have1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

  • This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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