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$40.5K

$88.2K

$158.5K

How much do serdes design engineer jobs pay per year?

As of Jul 27, 2026, the average yearly pay for serdes design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Serdes Design Engineer position, and why are they important?

A Serdes Design Engineer needs strong expertise in high-speed digital and analog circuit design, signal integrity, and a solid background in electrical engineering, typically with a relevant degree. Familiarity with industry tools such as Cadence, Synopsys, SPICE simulators, and hands-on experience with lab equipment are essential, while some positions value certifications in VLSI design or similar fields. Excellent problem-solving abilities, effective communication, and collaboration skills are important soft skills that set top candidates apart. These qualities are critical for ensuring reliable Serdes interface designs, troubleshooting complex issues, and working efficiently as part of multidisciplinary engineering teams.

What are some common challenges faced by Serdes Design Engineers, and how are they addressed?

Serdes Design Engineers commonly face challenges such as ensuring signal integrity at high data rates, managing power consumption, and mitigating electromagnetic interference. Addressing these issues typically involves close collaboration with layout, verification, and system engineering teams, as well as rigorous simulation and testing using specialized tools. Engineers must stay current with evolving standards and implement innovative solutions to meet strict performance and reliability requirements. This dynamic and collaborative environment fosters professional growth and the development of advanced technical skills.

What is a Serdes Design Engineer job?

A SerDes (Serializer/Deserializer) Design Engineer is responsible for designing, verifying, and optimizing high-speed data transmission circuits used in communication and computing systems. They work on developing physical layer interfaces, ensuring signal integrity, and minimizing power consumption. This role involves circuit design, simulation, layout, and collaboration with cross-functional teams to integrate SerDes IP into larger chip designs. Strong knowledge of analog and mixed-signal design, PCB modeling, and high-speed serial interfaces like PCIe, USB, or Ethernet is required.

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Serdes Design Engineer jobs near you
Infographic showing various Serdes Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Principal SerDes Design Engineer

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Posted 21 days ago

Job description

We are seeking an experienced SerDes Design Engineer to help deliver disruptive high-speed interconnect technology powering the next generation of AI infrastructure. In this role, you will lead the architecture and design of cutting-edge SerDes solutions for next-generation transceivers, driving innovations that enable higher bandwidth, lower power, and industry-leading performance for AI networking and optical connectivity.
Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON
What You Will Do:
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area (PPA)
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
What You Will Bring:
• Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills
Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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