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How much do per diem serdes design engineer jobs pay per year?

As of Jul 27, 2026, the average yearly pay for per diem serdes design engineer in the United States is $141,351.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $158,000.00 per year, depending on experience, location, and employer.
What cities are hiring for Per Diem Serdes Design Engineer jobs? Cities with the most Per Diem Serdes Design Engineer job openings:
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Per Diem Serdes Design Engineer jobs near you
Infographic showing various Per Diem Serdes Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $141,351 per year, or $68 per hour.

Principal SerDes Design Engineer

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

Posted 20 days ago

Job description

We are seeking an experienced SerDes Design Engineer to help deliver disruptive high-speed interconnect technology powering the next generation of AI infrastructure. In this role, you will lead the architecture and design of cutting-edge SerDes solutions for next-generation transceivers, driving innovations that enable higher bandwidth, lower power, and industry-leading performance for AI networking and optical connectivity.
Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON
What You Will Do:
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area (PPA)
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
What You Will Bring:
• Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills
Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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