PD Intern
San Jose, CA · On-site
... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...
PD Intern
San Jose, CA · On-site
... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...
PD Intern
San Jose, CA · On-site
... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...
Quick apply
PD Intern
San Jose, CA · On-site
... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...
FPGA Hardware Design Intern: RTL, Verilog & Prototyping
Dover, DE · On-site
$97K - $134K/yr
Internship Description This internship offers project-based learning in digital hardware and FPGA ... Participants will work on guided FPGA design exercises, from RTL development to hardware validation.
FPGA Hardware Design Intern: RTL, Verilog & Prototyping
Dover, DE · On-site
$97K - $134K/yr
Internship Description This internship offers project-based learning in digital hardware and FPGA ... Participants will work on guided FPGA design exercises, from RTL development to hardware validation.
Physical Design Engineer
Bristol, VA · On-site
$80 - $120/hr
Work closely with RTL and architecture teams to support design feasibility, constraints, and ... internships. * Familiarity with EDA tools for place & route, STA, and sign‑off. * Basic ...
Physical Design Engineer
Bristol, VA · On-site
$80 - $120/hr
Work closely with RTL and architecture teams to support design feasibility, constraints, and ... internships. * Familiarity with EDA tools for place & route, STA, and sign‑off. * Basic ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
Develop logic designs and RTL code for SoC designs, ensuring alignment with architectural and ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
SoC Design Engineer
Austin, TX · On-site
$122K - $232K/yr
Develop logic designs and RTL code for SoC designs, ensuring alignment with architectural and ... experience, internship experience and / or schoolwork/classes/research. The preferred ...
Principal job responsibilities include RTL design, verification, synthesis, timing optimization ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal job responsibilities include RTL design, verification, synthesis, timing optimization ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal job responsibilities include RTL design, verification, synthesis, timing optimization ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal job responsibilities include RTL design, verification, synthesis, timing optimization ... every stage - from internship to retirement and through life's most important moments. Our ...
Mixed Signal Logic Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
Mixed Signal Logic Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
RTL Intern
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
RTL Intern
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
Mixed Signal Logic Design Engineer
San Jose, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
Mixed Signal Logic Design Engineer
San Jose, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:
This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will ...
This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will ...
This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will ...
This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will ...
RTL Intern
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
Quick apply
RTL Intern
San Jose, CA · On-site
We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and ... We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
RTL design experience, synthesis, static-timing closure, formal verification, gate-level ... every stage - from internship to retirement and through life's most important moments. Our ...
RTL design experience, synthesis, static-timing closure, formal verification, gate-level ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal Digital Design Engineer
San Diego, CA · On-site
$144K/yr
RTL design experience, synthesis, static-timing closure, formal verification, gate-level ... every stage - from internship to retirement and through life's most important moments. Our ...
Principal Digital Design Engineer
San Diego, CA · On-site
$144K/yr
RTL design experience, synthesis, static-timing closure, formal verification, gate-level ... every stage - from internship to retirement and through life's most important moments. Our ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing ... Your successful track record of mentoring junior engineers and interns a huge plus. * A strong ...
Internship Rtl Design information
See salary details
$6.73 - $8.26
2% of jobs
$8.26 - $9.79
3% of jobs
$9.79 - $11.32
2% of jobs
$11.32 - $12.85
3% of jobs
$12.85 - $14.38
8% of jobs
$14.67 is the 25th percentile. Wages below this are outliers.
$14.38 - $15.91
32% of jobs
$15.91 - $17.44
15% of jobs
$18.73 is the 75th percentile. Wages above this are outliers.
$17.44 - $18.97
12% of jobs
$18.97 - $20.50
15% of jobs
$20.50 - $22.03
7% of jobs
$22.03 - $23.56
1% of jobs
$6
$16
$23
How much do internship rtl design jobs pay per hour?
As of Aug 22, 2026, the average hourly pay for internship rtl design in the United States is $16.33, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.
What is an internship RTL design?
An Internship in RTL (Register Transfer Level) Design involves working on digital circuit design using hardware description languages like Verilog or VHDL. Interns assist in designing, simulating, and verifying digital circuits, ensuring they meet performance and power requirements. They often work with FPGA or ASIC teams to validate designs and optimize hardware implementations. This role provides hands-on experience in hardware development and exposure to industry-standard tools like Synopsys, Cadence, or Xilinx.
What are the typical responsibilities of an internship RTL design?
As an RTL Design Intern, you will usually assist with the design, implementation, and verification of digital circuits using hardware description languages. Your daily work may include writing RTL code, debugging simulation results, collaborating with senior engineers, and participating in code and design reviews. You’ll also help with testbench creation, documentation, and possibly automate design tasks to support the larger engineering team. The role offers valuable hands-on experience and insight into the full design cycle, making it a great learning opportunity for those interested in digital hardware engineering.
What are the key skills and qualifications needed to thrive in the internship RTL design position?
To thrive as an RTL Design Intern, you need a solid understanding of digital design concepts, hardware description languages like Verilog or VHDL, and enrollment in or completion of a degree in electrical or computer engineering. Familiarity with simulation tools such as ModelSim or Synopsys VCS, and basic knowledge of EDA tools and version control systems, is typically expected. Strong analytical skills, attention to detail, and effective communication are highly valued soft skills in this role. These skills ensure you can efficiently contribute to design teams, troubleshoot issues, and communicate technical concepts clearly, all of which are critical for successful hardware development.
More about Internship Rtl Design jobs
What cities are hiring for Internship Rtl Design jobs?
Cities with the most Internship Rtl Design job openings:
What are the most commonly searched types of Rtl Design jobs?
The most popular types of Rtl Design jobs are:
What states have the most Internship Rtl Design jobs?
States with the most job openings for Internship Rtl Design jobs include:
What job categories do people searching Internship Rtl Design jobs look for?
The top searched job categories for Internship Rtl Design jobs are:
Internship
Re-posted 15 days ago
Job description
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Strong candidates may also have experience with
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Familiarity with numerical representations and functions (RTL)
- Familiarity with clocking and reset schemes (RTL/PD)
- UVM or formal verification experience (DV)
- Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.