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Internship Rtl Design Jobs in California (NOW HIRING)

Etched

PD Intern

San Jose, CA · On-site

... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...

Etched

PD Intern

San Jose, CA · On-site

... RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You may be a good fit if you have * Progress towards a Bachelor's, Master's, or PhD degree in electrical ...

Intel

Mixed Signal Logic Design Engineer

Santa Clara, CA · On-site

$122K - $232K/yr

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:

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Internship Rtl Design information

What are the key skills and qualifications needed to thrive in the Internship Rtl Design position, and why are they important?

To thrive as an RTL Design Intern, you need a solid understanding of digital design concepts, hardware description languages like Verilog or VHDL, and enrollment in or completion of a degree in electrical or computer engineering. Familiarity with simulation tools such as ModelSim or Synopsys VCS, and basic knowledge of EDA tools and version control systems, is typically expected. Strong analytical skills, attention to detail, and effective communication are highly valued soft skills in this role. These skills ensure you can efficiently contribute to design teams, troubleshoot issues, and communicate technical concepts clearly, all of which are critical for successful hardware development.

What are the typical responsibilities of an RTL Design Intern during their internship?

As an RTL Design Intern, you will usually assist with the design, implementation, and verification of digital circuits using hardware description languages. Your daily work may include writing RTL code, debugging simulation results, collaborating with senior engineers, and participating in code and design reviews. You’ll also help with testbench creation, documentation, and possibly automate design tasks to support the larger engineering team. The role offers valuable hands-on experience and insight into the full design cycle, making it a great learning opportunity for those interested in digital hardware engineering.

What is an Internship RTL Design job?

An Internship in RTL (Register Transfer Level) Design involves working on digital circuit design using hardware description languages like Verilog or VHDL. Interns assist in designing, simulating, and verifying digital circuits, ensuring they meet performance and power requirements. They often work with FPGA or ASIC teams to validate designs and optimize hardware implementations. This role provides hands-on experience in hardware development and exposure to industry-standard tools like Synopsys, Cadence, or Xilinx.

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Internship Rtl Design jobs near you
Senior Staff Design Engineer - PCIE/CXL Subsystem COE

Senior Staff Design Engineer - PCIE/CXL Subsystem COE

Marvell Technology, Inc.

Irvine, CA • On-site

Full-time

Life, Retirement

Re-posted 17 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Center of Excellence (COE), part of the Custom Cloud Solutions (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems - spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence.
By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle - sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon.
As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.
What You Can Expect
  • Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration
  • Collaborate closely with Architecture teams to translate requirements into robust RTL designs
  • Work with Design Verification teams on test-plan reviews, debug, and coverage closure
  • Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL
  • Support silicon bring-up and post-silicon debug, working with firmware and validation teams
  • Drive design quality improvements, coding best practices, and reuse across projects
  • Participate in design reviews, milestone reviews, and cross-functional technical discussions
  • Mentor junior designers and provide technical leadership within the PCIE/CXL design domain

What We're Looking For
Required Qualifications
  • Master's/bachelor's degree in Electronics/Electrical Engineering with 10+ years of relevant experience in RTL design
  • Proven experience delivering complex PCIE/CXL controllers or subsystems from architecture through RTL closure
  • Strong hands-on experience in System Verilog / Verilog RTL development
  • Expertise/Familiarity in PCIE/CXL specifications
  • Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
  • Solid grasp of Clocking, Resets, CDC/RDC, low-power techniques, and performance optimization
  • Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows
  • Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens
  • Proficient in scripting languages such as TCL / Perl / Python
  • Experience with version control systems such as GIT, SVN, etc.

Additional Qualifications
  • Experience on end-to-end PCIE/CXL subsystem RTL design execution and sign-off
  • Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms
  • Proficient in debugging functional and performance issues at subsystem and SoC levels
  • Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams
  • Prior experience mentoring engineers and providing technical leadership in a cross-functional environment

Expected Base Pay Range (USD)
135,900 - 201,130, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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