PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You ...
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PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns. You ...
$50/hr
As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating ... End-to-end physical design flow-from RTL handoff to final tapeout * Deep dive into timing, power ...
$50/hr
As a Physical Design Intern, you'll work hands-on from synthesis through tapeout, collaborating ... End-to-end physical design flow-from RTL handoff to final tapeout * Deep dive into timing, power ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$81 - $104/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$81 - $104/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Key Responsibilities Design and implement RTL for SoC-level blocks and subsystems used in HBM logic ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Key Responsibilities Design and implement RTL for SoC-level blocks and subsystems used in HBM logic ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Key Responsibilities Design and implement RTL for SoC-level blocks and subsystems used in HBM logic ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Key Responsibilities Design and implement RTL for SoC-level blocks and subsystems used in HBM logic ...
New
HBM SoC RTL Design AI-Driven Workflows
Folsom, CA · On-site
$145K/yr
Micron Technology invites a SoC Design Engineer Intern to contribute to the design, development ... implement robust, high-performance RTL blocks and subsystems. As part of the Heterogeneous ...
New
HBM SoC RTL Design AI-Driven Workflows
Folsom, CA · On-site
$145K/yr
Micron Technology invites a SoC Design Engineer Intern to contribute to the design, development ... implement robust, high-performance RTL blocks and subsystems. As part of the Heterogeneous ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$54 - $69/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$54 - $69/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. * Integrate ...
HBM SoC RTL Design AI-Driven Workflows
Folsom, CA · On-site
$145K/yr
Micron Technology invites a SoC Design Engineer Intern to contribute to the design, development ... implement robust, high-performance RTL blocks and subsystems. As part of the Heterogeneous ...
New
HBM SoC RTL Design AI-Driven Workflows
Folsom, CA · On-site
$145K/yr
Micron Technology invites a SoC Design Engineer Intern to contribute to the design, development ... implement robust, high-performance RTL blocks and subsystems. As part of the Heterogeneous ...
New
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
As a SoC Design Engineer Intern, you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Youll contribute to RTL design, simulations, and performance optimization for real-world AI ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... Youll contribute to RTL design, simulations, and performance optimization for real-world AI ...
Example teams and focus areas include: - RTL design for machine learning accelerators (Trainium ... As an ASIC Engineer Intern, you'll contribute to real chip development work, which may include ...
Example teams and focus areas include: - RTL design for machine learning accelerators (Trainium ... As an ASIC Engineer Intern, you'll contribute to real chip development work, which may include ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... You'll contribute to RTL design, simulations, and performance optimization for real-world AI ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
About the Role We are seeking a Digital Hardware Intern to support the design, verification, and ... You'll contribute to RTL design, simulations, and performance optimization for real-world AI ...
Example teams and focus areas include: - RTL design for machine learning accelerators (Trainium ... As an ASIC Engineer Intern, you'll contribute to real chip development work, which may include ...
Example teams and focus areas include: - RTL design for machine learning accelerators (Trainium ... As an ASIC Engineer Intern, you'll contribute to real chip development work, which may include ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
Job Summary This position is for a design verification/validation intern for Analog Mixed-Signal ... Ability to develop RTL and run Verilog simulations * Familiarity with FPGA development tools and ...
RFIC Design Intern
San Diego, CA · On-site
$31 - $42/hr
Exposure to digital design flow (RTL, synthesis, place and route, timing closure) is a plus * Tape-out experience preferred * Exposure to RF measurement equipment such as spectrum analyzers and ...
New
RFIC Design Intern
San Diego, CA · On-site
$31 - $42/hr
Exposure to digital design flow (RTL, synthesis, place and route, timing closure) is a plus * Tape-out experience preferred * Exposure to RF measurement equipment such as spectrum analyzers and ...
New
RFIC Design Intern
San Diego, CA · On-site
$31 - $42/hr
Exposure to digital design flow (RTL, synthesis, place and route, timing closure) is a plus * Tape-out experience preferred * Exposure to RF measurement equipment such as spectrum analyzers and ...
RFIC Design Intern
San Diego, CA · On-site
$31 - $42/hr
Exposure to digital design flow (RTL, synthesis, place and route, timing closure) is a plus * Tape-out experience preferred * Exposure to RF measurement equipment such as spectrum analyzers and ...
Rtl Design Intern information
What is an RTL design intern?
RTL Design Interns are students or recent graduates who assist with the design and verification of digital circuits at the Register Transfer Level (RTL) using hardware description languages like Verilog or VHDL. They typically work under the supervision of experienced engineers to help develop, simulate, and debug digital logic blocks that form the basis of processors, ASICs, or FPGAs. This internship provides hands-on experience in digital design, exposure to industry-standard tools, and an understanding of the full hardware development lifecycle.
What are some typical projects or tasks that an RTL design intern might work on during their internship?
As an RTL Design Intern, you can expect to assist with creating and verifying register-transfer level (RTL) code for digital circuits, which may involve writing code in hardware description languages like Verilog or VHDL. Interns often support senior engineers by running simulations, debugging logic errors, and documenting design specifications. You may also participate in design reviews and collaborate with verification, physical design, and software teams to ensure the design meets functional and timing requirements. This hands-on experience gives interns valuable insight into the full chip design cycle and helps build foundational skills for a career in hardware engineering.
What are the key skills and qualifications needed to thrive as an RTL design intern, and why are they important?
To thrive as an RTL Design Intern, you need a solid understanding of digital logic design, Verilog or VHDL programming, and coursework in computer architecture or electrical engineering. Familiarity with simulation tools like ModelSim, synthesis tools such as Synopsys or Cadence, and version control systems is highly valuable. Strong problem-solving abilities, attention to detail, and effective communication skills help you collaborate and troubleshoot design challenges. These skills and qualities are crucial for ensuring accurate, efficient hardware designs and successful integration within engineering teams.
What is the difference between Rtl Design Intern vs Digital Design Intern?
| Aspect | Rtl Design Intern | Digital Design Intern |
|---|---|---|
| Required Credentials | Enrolled in Electrical Engineering, Computer Engineering, or related fields | Enrolled in Graphic Design, Visual Arts, or related fields |
| Work Environment | Semiconductor, electronics, or hardware companies | Advertising agencies, media companies, or tech firms |
| Industry Usage | Used in chip design, FPGA development, ASIC projects | Used in branding, UI/UX, digital media projects |
Rtl Design Interns focus on hardware description languages and chip design, working in electronics and semiconductor environments. Digital Design Interns typically work on visual and user interface projects in media or tech companies. While both roles involve design skills, they serve different industries and technical focuses, making them distinct internship paths within the broader digital and hardware design fields.
What are the most commonly searched types of Rtl Design jobs in California?
The most popular types of Rtl Design jobs in California are:
What are popular job titles related to Rtl Design Intern jobs in California?
For Rtl Design Intern jobs in California, the most frequently searched job titles are:
What job categories do people searching Rtl Design Intern jobs in California look for?
The top searched job categories for Rtl Design Intern jobs in California are:
What cities in California are hiring for Rtl Design Intern jobs?
Cities in California with the most Rtl Design Intern job openings:
Internship
Re-posted 29 days ago
Job description
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Strong candidates may also have experience with
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Physical Design intern for Etched, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Familiarity with numerical representations and functions (RTL)
- Familiarity with clocking and reset schemes (RTL/PD)
- UVM or formal verification experience (DV)
- Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.