Internship Rtl Design Jobs in California (NOW HIRING)

Job Details:Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Intel's multiprotocol SerDes design team is hiring for a critical design position in Santa Clara office to ensure continued support of some of the world's most versatile next-generation products. We have a long track record of silicon success over multiple technology nodes. Supporting multi-national High speed SerDes team, we are hiring a technically experienced Logic Design Engineer. The key responsibilities of this person include the following:Logic design of High Speed SerDes Design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participating in the definition of architecture and microarchitecture features of the block being designed. Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supporting SoC customers to ensure high quality integration and verification of the IP block. Driving quality assurance compliance for smooth IP SoC handoff. The Logic Design Engineer should possess the following attributes:Excellent communication: Expected to drive clarity across partners, managers.Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can. Strong analytical and problem solving skills with the ability to independently draw conclusions.Qualifications:What we need to see (Minimum Qualifications):Bachelors in Electrical/Computer Engineering and 8+ years of experience -OR- Master's degree in Electrical/Computer Engineering with 6+ years of industry experience in:Minimum 5+ years of experience in Mixed signal design specifically High Speed SerDes design and architectureDetailed knowledge of SerDes PMA and PCS layers Experienced with post-silicon validation and support of the High Speed SerDes IPReading and interpreting technical specs to come up with Microarchitecture and implement RTL design in System Verilog.Computer system architecture and Digital Design.OVM/UVM methodology to interact with the Validation designers for Val content development. How to Stand out (Preferred Qualifications):Experience with automated Place-and-route (APR) team to convey constraints and work together to close timing issuesScripting in at least one of the following interpreted language (e.g. TCL, Perl, Python, Ruby) Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:Business group:As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.