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Intern Soc Design Engineer Jobs (NOW HIRING)

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

Wireless SoC Design Engineer

San Diego, CA · On-site

$139K - $258K/yr

... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...

... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ...

HBM SoC Design Engineer

Folsom, CA · On-site

$146K - $309K/yr

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work ...

Debug SoC Design Engineer

Irvine, CA · On-site

$120K - $210K/yr

You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...

Debug SoC Design Engineer

Irvine, CA · On-site

$120K - $210K/yr

You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...

Debug SoC Design Engineer

Irvine, CA · On-site

$120K - $210K/yr

You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

SoC Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of nextgeneration HBM SoC logic die. You will work ...

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Intern Soc Design Engineer information

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$9

$19

$36

How much do intern soc design engineer jobs pay per hour?

As of Jun 5, 2026, the average hourly pay for intern soc design engineer in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is the difference between Intern Soc Design Engineer vs Intern Hardware Design Engineer?

AspectIntern Soc Design EngineerIntern Hardware Design Engineer
Required SkillsDigital/analog circuit design, FPGA, PCB layout, scriptingCircuit schematic, PCB design, component selection, testing
Work EnvironmentSemiconductor companies, electronics firms, R&D labsConsumer electronics, industrial equipment, R&D teams
Common UsageFocus on system-on-chip (SoC) architecture and integrationFocus on hardware components and circuit implementation

Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.

What cities are hiring for Intern Soc Design Engineer jobs? Cities with the most Intern Soc Design Engineer job openings:
What are the most commonly searched types of Soc Design Engineer jobs? The most popular types of Soc Design Engineer jobs are:
What states have the most Intern Soc Design Engineer jobs? States with the most job openings for Intern Soc Design Engineer jobs include:
SoC Design Engineer

SoC Design Engineer

OMNIVISION

Santa Clara, CA

Full-time

Posted 28 days ago


Job description

Responsibilities :
  • Image sensor control or processing function design and verification
  • High speed interface (USB/MIPI) design and verification
  • Full-chip integration and verification
  • Chip bring-up, validation, and debugging
  • Participate in the FPGA development
  • Architecture, registers, interface and design documentation.            
Qualifications :
  • PhD or MSEE with some experience of digital design 
  • Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality
  • Knowledge of high performance and low power design techniques.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of SOC architecture.
  • Knowledge of assertion-based formal verification is a plus
  • Image processing/DSP knowledge is a plus
Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
EOE/Minorities/Females/Vet/Disability  Â