Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Quick apply
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Quick apply
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
San Jose, CA · Remote
$55 - $60/hr
RTL Design Engineer - Wireless SoC Location: Remote Job Type: Contract We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will ...
New
Quick apply
San Jose, CA · Remote
$55 - $60/hr
RTL Design Engineer - Wireless SoC Location: Remote Job Type: Contract We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will ...
New
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
San Diego, CA · On-site
$139K - $258K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
San Diego, CA · On-site
$139K - $258K/yr
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
San Diego, CA · On-site
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ...
San Diego, CA · On-site
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified ...
As a Software Engineer, SOC Design Methodology, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package ...
As a Software Engineer, SOC Design Methodology, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package ...
Folsom, CA · On-site
$146K - $309K/yr
As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work ...
Folsom, CA · On-site
$146K - $309K/yr
As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work ...
As a Software Engineer, SOC Design Methodology, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package ...
As a Software Engineer, SOC Design Methodology, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Irvine, CA · On-site
$120K - $210K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Quick apply
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
$146K - $309K/yr
As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of nextgeneration HBM SoC logic die. You will work ...
$146K - $309K/yr
As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of nextgeneration HBM SoC logic die. You will work ...
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
| Aspect | Intern Soc Design Engineer | Intern Hardware Design Engineer |
|---|---|---|
| Required Skills | Digital/analog circuit design, FPGA, PCB layout, scripting | Circuit schematic, PCB design, component selection, testing |
| Work Environment | Semiconductor companies, electronics firms, R&D labs | Consumer electronics, industrial equipment, R&D teams |
| Common Usage | Focus on system-on-chip (SoC) architecture and integration | Focus on hardware components and circuit implementation |
Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.
Sourced by ZipRecruiter
Software development
1,001 - 5,000 Employees
Santa Clara, CA, US
1995