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Intern Soc Design Engineer Jobs in Chicago, IL (NOW HIRING)

Cadence Design Systems Inc.

Lead Design Engineer

Cary, IL

$104K - $136K/yr

... SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs ... Interface with Front End RTL design teams and Back End Verification teams Position Requirements ...

IMEG

Lighting Design Intern | Chicago, IL

Chicago, IL · On-site +1

$22 - $24/hr

... Engineering, or Theatrical Lighting Design, Interior Design or equivalent required Strong interest ... intern once became our Virtual Reality leader Exposure across disciplines and offices at a 100 ...

New

SWE Solutions

Construction Engineer Intern

Lombard, IL · On-site

$20 - $30/hr

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

SWE Solutions

Construction Engineer Intern

Lombard, IL · On-site

$20 - $30/hr

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

SWE Solutions

Construction Engineer Intern

Lombard, IL

$20 - $30/hr

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

Jump Trading

Digital Modem Engineer

Chicago, IL · On-site

$150K - $250K/yr

We design, develop, and deploy technologies that change our world, fund start-ups across industries ... both intern and full-time opportunities. Benefits * Discretionary bonus eligibility * Medical ...

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All JobsIntern Soc Design Engineer JobsIntern Soc Design Engineer Jobs in Chicago, IL

Intern Soc Design Engineer information

See Chicago, IL salary details

$9

$19

$37

How much do intern soc design engineer jobs pay per hour?

As of Aug 27, 2026, the average hourly pay for intern soc design engineer in Chicago, IL is $19.96, according to ZipRecruiter salary data. Most workers in this role earn between $14.86 and $22.31 per hour, depending on experience, location, and employer.

What is the difference between Intern Soc Design Engineer vs Intern Hardware Design Engineer?

AspectIntern Soc Design EngineerIntern Hardware Design Engineer
Required SkillsDigital/analog circuit design, FPGA, PCB layout, scriptingCircuit schematic, PCB design, component selection, testing
Work EnvironmentSemiconductor companies, electronics firms, R&D labsConsumer electronics, industrial equipment, R&D teams
Common UsageFocus on system-on-chip (SoC) architecture and integrationFocus on hardware components and circuit implementation

Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.

What are the most commonly searched types of Soc Design Engineer jobs in Chicago, IL?

The most popular types of Soc Design Engineer jobs in Chicago, IL are:

What cities near Chicago, IL are hiring for Intern Soc Design Engineer jobs?

Cities near Chicago, IL with the most Intern Soc Design Engineer job openings:

Intern Soc Design Engineer jobs near you
Infographic showing various Intern Soc Design Engineer job openings in Chicago, IL as of July 2026, with employment types broken down into 17% Internship, 67% Full Time, 8% Part Time, and 8% Temporary. Highlights an 92% In-person, and 8% Hybrid job distribution, with an average salary of $41,519 per year, or $20 per hour.

Lead Design Engineer

Cary, IL

Cadence Design Systems Inc.
Software Development • 5 - 10K employees

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

34th of 246 rated software companies

Good employer

Respectful managers

Uninterrupted breaks

Learn more about Cadence Design Systems Inc.external

$104K - $136K/yr

Full-time

Re-posted 6 days ago

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadenceis a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Job Responsibility

Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.

  • Work on RTL synthesis and floorplanning
  • Build clock trees and perform optimizations
  • Close timing, IR drop and physical verification
  • Review and Document designs for taping out
  • Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

  • BSdegreeinElectricalEngineeringwithaminimumof5yearsofexperienceORMSwithaminimumof3yearsofexperience
  • Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
  • Experience with advanced technologies like 5nm, 3ns and 2nm nodes
  • Experience using Linux servers, Script development using Shell/Perl/TCL/Python
  • Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.
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