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Intern Soc Design Engineer Jobs in Chicago, IL (NOW HIRING)

Design Engineer I

Cary, IL · On-site

$88K - $165K/yr

... Cadence Design Systems Palladium platform... As such we are seeking an experienced DFT engineer ... Define and implement SoC level DFT architecture for large and complex designs. * Develop, integrate ...

Lead Design Engineer

Cary, IL · On-site

$104K - $136K/yr

... SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs ... Interface with Front End RTL design teams and Back End Verification teams Position Requirements ...

Design Verification Engineer

Chicago, IL · On-site

$140K - $171K/yr

Design Verification Engineer We are seeking a detail-oriented Design Verification Engineer to manage and oversee the daily operations of our ASIC/SoC verification workflows and testbench architecture.

... Engineering, or Theatrical Lighting Design, Interior Design or equivalent required • Strong ... at IMEG, an intern once became our Virtual Reality leader • Exposure across disciplines and ...

... Engineering, or Theatrical Lighting Design, Interior Design or equivalent required Strong interest ... intern once became our Virtual Reality leader Exposure across disciplines and offices at a 100 ...

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

The intern will assist in a variety of tasks related to the planning, execution, and documentation ... design plans, specifications, and safety standards. * Support engineers in preparing project ...

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Intern Soc Design Engineer information

See Chicago, IL salary details

$9

$19

$37

How much do intern soc design engineer jobs pay per hour?

As of Sep 4, 2026, the average hourly pay for intern soc design engineer in Chicago, IL is $19.96, according to ZipRecruiter salary data. Most workers in this role earn between $14.86 and $22.31 per hour, depending on experience, location, and employer.

What is the difference between Intern Soc Design Engineer vs Intern Hardware Design Engineer?

AspectIntern Soc Design EngineerIntern Hardware Design Engineer
Required SkillsDigital/analog circuit design, FPGA, PCB layout, scriptingCircuit schematic, PCB design, component selection, testing
Work EnvironmentSemiconductor companies, electronics firms, R&D labsConsumer electronics, industrial equipment, R&D teams
Common UsageFocus on system-on-chip (SoC) architecture and integrationFocus on hardware components and circuit implementation

Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.

What are the most commonly searched types of Soc Design Engineer jobs in Chicago, IL?

The most popular types of Soc Design Engineer jobs in Chicago, IL are:

What cities near Chicago, IL are hiring for Intern Soc Design Engineer jobs?

Cities near Chicago, IL with the most Intern Soc Design Engineer job openings:

Infographic showing various Intern Soc Design Engineer job openings in Chicago, IL as of July 2026, with employment types broken down into 17% Internship, 67% Full Time, 8% Part Time, and 8% Temporary. Highlights an 92% In-person, and 8% Hybrid job distribution, with an average salary of $41,519 per year, or $20 per hour.

Solution Director- SOC & ASIC Design Services

Pump Dynamics

Mundelein, IL • On-site

Other

This job post has expired 4 days ago. Applications are no longer accepted.


Job description

Scope & Responsibilities

Our client, a leading global technology and engineering services organization, is seeking a senior technical leader to define and shape solution strategy across complex SoC and ASIC design engagements.

This is a senior individual contributor role serving as a primary technical authority in pre-sales and solutioning environments. The leader will partner directly with semiconductor clients to shape pursuit strategy, lead technical discovery, architect solutions, and ensure proposals are grounded in credible engineering and delivery frameworks. This role does not carry a sales quota.

Key Responsibilities

  • Lead technical solutioning for ASIC and SoC design pursuits, from initial discovery and scoping through proposal development and client presentations.
  • Define engagement models and delivery architectures spanning RTL design, DFT, physical design, signoff, verification, and tape-out support.
  • Develop differentiated technical solutions across synthesis, place-and-route, functional verification, formal verification, and low-power design.
  • Engage directly with chip architects, design leaders, and engineering executives to understand technical requirements, program objectives, and tool environments.
  • Develop reusable solution patterns and reference architectures based on successful client engagements.
  • Contribute thought leadership around AI-assisted semiconductor design, advanced-node tape-out readiness, chiplets, and multi-die architectures.

Key Selection Criteria

Required

  • 15+ years of hands-on ASIC and/or SoC design experience, with deep expertise in at least two areas:
  • RTL / microarchitecture
  • Design for Test (DFT)
  • Physical design
  • Functional verification (UVM/SVA)
  • Low-power design (CPF/UPF)
  • Demonstrated experience in a pre-sales, solution architecture, consulting, or client-facing technical leadership role, ideally within an engineering services, semiconductor, or EDA environment.
  • Strong command of major EDA ecosystems, including Synopsys, Cadence, and/or Siemens EDA.
  • Experience with advanced semiconductor process nodes, ideally 7nm and below.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, VLSI Design, or a related technical discipline.

Preferred

  • Experience with chiplet architectures, UCIe, and/or multi-die integration.
  • Familiarity with AI/ML accelerator architectures, NPUs, and inference-engine design challenges.
  • Experience translating highly complex semiconductor engineering requirements into client-facing solutions, architectures, and delivery models.

Confidentiality

This is a confidential executive search. Additional information regarding the organization, reporting structure, and broader mandate will be shared with qualified candidates during the search process.