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Part Time Soc Design Engineer Jobs (NOW HIRING)

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their ... This is a fully remote, part-time engagement requiring approximately 20-40 hours per week ...

Saratech, Inc.

Design Engineer

Mission Viejo, CA

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech

Design Engineer

Mission Viejo, CA · Remote

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech

Design Engineer

Mission Viejo, CA · On-site

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI · On-site

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

Apple

Cellular ASIC Design Engineer

Austin, TX · On-site

... on-chips (SoC). Your role will be pivotal in ensuring that Apple products and services can ... Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

Arcadis

Roadway Design Engineer

Detroit, MI · On-site

$90K - $110K/yr

As the Lead Roadway Design Engineer , you will play a pivotal role in overseeing and managing ... Arcadis offers benefits for full time and part time positions. These benefits include medical ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

W3Global Inc.

Electrical Design Engineer

Southlake, TX

$75K - $85K/yr

About the Role Our client is seeking an experienced Electrical Design Engineer to join a dynamic ... part-time work. A degree is not required for this position. Every project is custom-designed ...

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Part Time Soc Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do part time soc design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for part time soc design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Soc Design Engineer jobs? The most popular types of Soc Design Engineer jobs are:
Part Time Soc Design Engineer jobs near you

ASIC/SoC Design & Verification Engineer

Weekday AI

Remote

$70 - $100/hr

Part-time

Posted 9 days ago

Job description

This role is for one of our clients
Compensation: $70-$100 per hour
Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.
Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.
This is a fully remote, part-time engagement requiring approximately 20-40 hours per week, depending on your availability.
Requirements
Key Responsibilities
  • Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
  • Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
  • Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
  • Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
  • Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
  • Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.
Required Qualifications
  • Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
  • Strong proficiency in SystemVerilog and Verilog.
  • Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
  • Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
  • Deep expertise in one or more of the following areas:
    • RTL Design and Microarchitecture
    • Functional Verification (UVM, SVA, Cocotb, testbench development)
    • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
    • Formal Verification and Coverage Closure
    • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
    • Analog/Mixed-Signal Design Verification
    • Hardware Specification Development and Technical Documentation
  • Ability to commit 20-40 hours per week with reliable weekday availability.
  • Strong written communication skills and the ability to work independently in a remote environment.
Preferred Qualifications
  • Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
  • Graduate research or industry experience in semiconductor design, verification, or computer architecture.
  • Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
  • Experience mentoring engineers or reviewing complex technical designs.
Why Join
  • Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
  • Apply your practical chip design and verification expertise to improve the next generation of AI models.
  • Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
  • Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.
Equal Opportunity
We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.
Contract & Engagement Details
  • Independent contractor engagement.
  • Fully remote with flexible working hours.
  • Expected commitment of approximately 20-40 hours per week.
  • Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
  • Work does not require access to confidential or proprietary information from any current or former employer.
  • Payments are issued weekly based on approved work completed.
  • At this time, we are unable to support H1-B or STEM OPT candidates.

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