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Part Time Soc Design Engineer Jobs (NOW HIRING)

Futran Tech Solutions Pvt. Ltd.

Physical Design Engineer

$139K - $143K/yr

Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have ... Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys ...

Saratech

Design Engineer

Mission Viejo, CA · Remote

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech

Design Engineer

Mission Viejo, CA · On-site

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Saratech, Inc.

Design Engineer

Mission Viejo, CA

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design team with various support duties such as CAD modeling, part model check reviews, industry standard ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI · On-site

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Harley-Davidson

Senior Design Engineer

Wauwatosa, WI · On-site

Senior Design Engineer Job Function: Engineering Location: PDC Workplace Category: Onsite Company ... Harley-Davidson Motor Company Full or Part-Time: Full Time Shift: SHIFT1 In 1903, out of a small ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

Apple

Cellular ASIC Design Engineer

Austin, TX · On-site

... on-chips (SoC). Your role will be pivotal in ensuring that Apple products and services can ... Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

Arcadis

Roadway Design Engineer

Detroit, MI · On-site

$90K - $110K/yr

As the Lead Roadway Design Engineer , you will play a pivotal role in overseeing and managing ... Arcadis offers benefits for full time and part time positions. These benefits include medical ...

Apple

Cellular ASIC Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co ...

W3Global Inc.

Electrical Design Engineer

Southlake, TX

$75K - $85K/yr

About the Role Our client is seeking an experienced Electrical Design Engineer to join a dynamic ... part-time work. A degree is not required for this position. Every project is custom-designed ...

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Part Time Soc Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do part time soc design engineer jobs pay per year?

As of Jul 17, 2026, the average yearly pay for part time soc design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Soc Design Engineer jobs? The most popular types of Soc Design Engineer jobs are:
Part Time Soc Design Engineer jobs near you

Physical Design Engineer

Futran Tech Solutions Pvt. Ltd.

Remote

$139K - $143K/yr

Part-time

Re-posted 29 days ago

Job description

Job Description:
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening)
Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus, ICC2).
  • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 7nm and lower technology nodes.
  • Must have hands-on experience on PnR Suite from Synopsys/Cadence(Innovus, ICC2).
  • Strong experience on Static Timing Analysis(PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification(Calibre).
  • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.
  • Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
  • Good Customer interaction, Communication and Teamwork skills.
  • Should have experience in handling >5M instance count, 1.5GHz frequency designs.
  • Good to have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.

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