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Intern Soc Design Engineer Jobs in Arizona (NOW HIRING)

Physical Design Engineer

Phoenix, AZ

$135K - $139K/yr

Perform physical design implementation of custom IP and SoC designs, covering all aspects of the ... Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field ...

Physical Design Engineer

Phoenix, AZ ยท On-site

$135K - $139K/yr

... SoC design Min. * Qualifications: 0-1 yrs of exp. Enginner - CL11 & CL10 Master's degree in Electrical Eng. or Comp. Science RTL2GDSII exp. on advanced tech. nodes (7nm and below) Exp. w/low power ...

Principal Digital Design Engineer

Chandler, AZ ยท On-site +1

$200K - $250K/yr

About the Role We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components.

RTL Design Engineer

Chandler, AZ ยท On-site

$127K - $203K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Generate timing constraints for Synthesis and STA at the block-level and SoC top-level. * Drive ...

RTL Design Engineer

Chandler, AZ ยท On-site

$127K - $203K/yr

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Generate timing constraints for Synthesis and STA at the block-level and SoC top-level. * Drive ...

Physical Design Engineer

Phoenix, AZ ยท On-site

$91K - $149K/yr

In this role, you will be at the forefront of designing custom IP and SoC implementations ... design OR a Master's degree in Electrical Engineering, Computer Engineering, or a related ...

Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Staff Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Senior Digital Design Engineer

Chandler, AZ ยท On-site

$133K/yr

In this role, you will contribute to the design of system-on-chip (SoC) devices, digital signal ... Degree in Electrical Engineering, Computer Engineering, or a related technical field. * Bachelor ...

Supports SoC customers to ensure highquality integration of the CPU block. Qualifications: Minimum ... tools (Design Compiler, Genus)oScripting languages (Python, Perl, TCL)Preferred ...

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Showing results 1-20

Intern Soc Design Engineer information

What is the difference between Intern Soc Design Engineer vs Intern Hardware Design Engineer?

AspectIntern Soc Design EngineerIntern Hardware Design Engineer
Required SkillsDigital/analog circuit design, FPGA, PCB layout, scriptingCircuit schematic, PCB design, component selection, testing
Work EnvironmentSemiconductor companies, electronics firms, R&D labsConsumer electronics, industrial equipment, R&D teams
Common UsageFocus on system-on-chip (SoC) architecture and integrationFocus on hardware components and circuit implementation

Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.

What cities in Arizona are hiring for Intern Soc Design Engineer jobs? Cities in Arizona with the most Intern Soc Design Engineer job openings:

Senior FPGA Design Engineer

COMTECH TELECOMMUNICATIONS

Chandler, AZ โ€ข On-site

$101K - $136K/yr

Full-time

Re-posted 9 days ago


Job description


Job Title: Senior FPGA Engineer III

Department: Engineering->Platforms->FPGA SoC Group

Reports To: Director, Platforms

FLSA Status: Exempt

Last Modified: 9/10/2025

Level: T3

Location Chandler, AZ – Onsite 5 Days a week

Company Overview

Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com.
We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply.


Position Summary

Senior FPGA Designer with experience in the entire design flow for complex FPGA’s.

Responsibilities

  • Design, develop, document, debug and test FPGA SoC systems; including:
    1. IP Integration into FPGA Projects (synthesis/implementation)
    2. High-Performance FPGA IP (VHDL/SystemVerilog)
    3. Userspace Drivers for FPGA IP (C++)
    4. Firmware for Embedded Microcontrollers (C)
  • Utilize strong communication skills to effectively work and communicate with team members and engineering management.

Qualifications

  • Strong digital design engineer with FPGA/ASIC SoC design experience
  • Strong FPGA Implementation with Altera Quartus or Xilinx Vivado
  • Experience designing/debugging SoC systems with AMBA-compliant AXI and APB interfaces
  • Experience designing fmax-optimized, high-throughput, pipelined AXI-Stream IP
  • Capable of creating RTL simulations to identify and resolve most issues before hardware tests
  • Knowledgeable in Static Timing Analysis (STA) and Synopsis Design Constraints (SDC)
  • Experience analyzing STA reports and post-synth netlist/placement to resolve failing paths
  • Experience contributing to schematic capture and layout for FPGA portions of PCB designs
  • Experience implementing at least one Gigabit Transceiver Protocol:
    1. PCI Express, Interlaken, USB SuperSpeed
    2. 1000BASE-X/SGMII, 10GBASE-R, 40GBASE-4, 100GBASE-R4
  • Experience implementing Network Protocols, such as:
    • L1: IEEE 802.3, Cisco, Q/SFP+ MSA standards for Ethernet (1G to 100G)
    • L2/L3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
    • L4: VITA 49.2, IEEE-ISTO 4900 Digital IF Interoperability Standard (DIFI) and/or eCPRi
      (Highly Desired)
  • Proficient in SW development with C, C++ and GIT version control
  • Proficient in Microsoft Office Tools (Word, Excel, PowerPoint, Visio, etc.)
  • Demonstrated experience supporting multi-disciplinary, cross functional and matrixed teams

Desired Qualifications

  • Working knowledge of digital IF streams such as VITA 49.2, DIFI and/or eCPRi (Highly Desired)
  • Working knowledge of Embedded Linux: Kernel / Yocto / U-Boot / DeviceTree
  • Working knowledge with SATCOM waveforms like DVB-S2X and/or 5G NTN 3GPP Rel 17/18
  • Working knowledge of communication networks and security within a zero-trust environment
  • Experience with Partial Reconfiguration/DFX or PCIe CvP
  • Possess an active DoD clearance or demonstrate readiness to obtain one

Education

  • Bachelors in Electrical or Computer Engineering (or related degree).

Experience:

  • 5+ years of FPGA/ASIC SoC design experience.


Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.