ZipRecruiter

Log In

1

Ic Layout Design Engineer Jobs in Oregon (NOW HIRING)

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

$210K/yr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Apple

Circuit Design Engineer - Library

Beaverton, OR

$142K - $263K/yr

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

Apple

Circuit Design Engineer - Library

Beaverton, OR

$142K - $263K/yr

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

AST SpaceMobile

Mechanical Design Engineer

OR · On-site +1

$75K - $102K/yr

This role is responsible for structural architecture layout, primary and secondary structure design ... Bachelor's degree in mechanical engineering, aerospace engineering, or a related technical field ...

Noralogic Inc

Physical Design Engineer

Hillsboro, OR · On-site

$148K - $152K/yr

Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... of layout tasks, analysis of late changing process Additional Skills and or education: The ...

Noralogic Inc

Physical Design Engineer

Hillsboro, OR · On-site

$148K - $152K/yr

Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... of layout tasks, analysis of late changing process Additional Skills and or education: The ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR

$210K/yr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Apple Inc.

SerDes Circuit Design Engineer

Beaverton, OR · On-site

$140 - $210/hr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Noralogic Inc

Structural Design Engineer

Hillsboro, OR · On-site

Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... converged layout. This will also include, but not be limited to, meeting timing, performance ...

previous page

Showing results 41-60

All JobsIc Layout Design Engineer JobsIc Layout Design Engineer Jobs in Oregon

Ic Layout Design Engineer information

See Oregon salary details

$47.6K

$127.8K

$196.1K

How much do ic layout design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for ic layout design engineer in Oregon is $127,771.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,200.00 and $152,200.00 per year, depending on experience, location, and employer.

What does an IC layout design engineer do?

An IC Layout Design Engineer is responsible for creating the physical design of integrated circuits (ICs) based on schematic designs. They ensure optimal placement and routing of transistors and interconnections while meeting performance, power, and area constraints. They work closely with circuit designers and verification engineers to ensure manufacturability and compliance with design rules. Tools like Cadence Virtuoso or Mentor Graphics are commonly used in this role.

What are the key skills and qualifications needed to thrive as an IC layout design engineer?

To thrive as an IC Layout Design Engineer, you need strong expertise in analog and/or digital IC layout, semiconductor device physics, and an educational background in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and proficiency with layout verification techniques (like DRC and LVS) are typically required. Exceptional attention to detail, effective communication, and the ability to collaborate closely with circuit design teams are valuable soft skills. These skills are essential to ensure the successful design, optimization, and integration of complex integrated circuits in high-performance environments.

What are the common challenges faced by IC layout design engineers on the job?

IC Layout Design Engineers often encounter challenges such as meeting strict design specification requirements, managing complex circuitry within limited silicon area, and ensuring layouts comply with manufacturing constraints. They may need to troubleshoot and resolve issues with DRC/LVS errors, work under tight project deadlines, and adapt quickly to changes in design parameters. Close collaboration with circuit design engineers and verification teams is common, requiring strong teamwork and effective communication. These challenges make the role dynamic and can provide excellent opportunities to develop specialized skills and advance into lead or principal engineering positions over time.

What are the most commonly searched types of Ic Layout Design Engineer jobs in Oregon?

The most popular types of Ic Layout Design Engineer jobs in Oregon are:

What are popular job titles related to Ic Layout Design Engineer jobs in Oregon?

For Ic Layout Design Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Ic Layout Design Engineer jobs in Oregon look for?

The top searched job categories for Ic Layout Design Engineer jobs in Oregon are:

Ic Layout Design Engineer jobs near you
Infographic showing various Ic Layout Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 94% Full Time, and 6% Contract. Highlights an 87% In-person, and 13% Remote job distribution, with an average salary of $127,771 per year, or $61.4 per hour.

SerDes Circuit Design Engineer

Apple

Beaverton, OR • On-site

$210K/yr

Full-time

Re-posted 6 days ago

Apple rating

8.1

Company rating: 8.1 out of 10

Based on 683 frontline employees who took The Breakroom Quiz

6th of 30 rated technology retailers

Job description

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple's world-leading system-on-chip (SOC).
In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create and execute on state-of-the-art IPs key to Apple's products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With redefining the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.
If you have strong fundamentals and a track record of tackling technical challenges, you are passionate about learning new skills and improving the value of your work, and you like to be tuned to the bigger-picture while diving deeply into the details to innovate and tackle problems- we invite you to join and grow with our team!
Description
You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, high-speed analog signal chain, mixed-signal calibration and algorithms) with best in class power, performance, and area (PPA).
You will work with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create block-level specifications and execute on transistor-level implementation and behavioral modeling. You will drive mask design to implement layout view of designs. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress and discuss new ideas making it a lively and interactive work environment.
Minimum Qualifications
Minimum requirement of a bachelors degree
Preferred Qualifications
Deep understanding of analog mixed-signal design with experience in high-speed serial links.
Understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
Understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
Good grasp and understanding of digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)
Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design concepts
Knowledge of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 64+ Gbps NRZ and PAM applications
Knowledge of CDR architectures and implementations
Knowledge of lab equipment and testing
Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)
Hands-on experience in advanced CMOS technologies, design with FinFet technology
Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)
Experience in lab testing of high-speed serial I/O, debug and data analysis techniques
Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY)
Skills in scripting and automation to enhance efficiency are highly desirable

What Apple employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apple logo

About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

View All Apple Jobs

Apply