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Internship Ic Layout Design Engineer Jobs in Oregon

Intel Corporation

Analog Layout Design Engineer

Hillsboro, OR · On-site

$220K/yr

  • Medical

  • Retirement

  • PTO

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join our diverse and inclusive team. As a critical contributor to our design ecosystem, you will drive ...

Intel

Analog Layout Design Engineer

Hillsboro, OR

$220K/yr

  • Medical

  • Retirement

  • PTO

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join our diverse and inclusive team. As a critical contributor to our design ecosystem, you will drive ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR

  • Medical

  • Retirement

  • PTO

Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory ... PhD with 1-2 years of professional experience gained through either internships or full-time ...

Biotronik

Staff IC Design Engineer, Analog

Lake Oswego, OR · On-site

$207K/yr

Staff IC Design Engineer, Analog The Staff IC Design Engineer provides advanced technical expertise ... Solid understanding of circuit building blocks and layout techniques for ultra-low-power design ...

Nvidia

Senior Mask Design Engineer - Hardware

OR · On-site +1

Propose layout design trade-offs to the PTL for resolution and implementation. What we need to see: * Hold a B.S. Electrical Engineering or equivalent experience * Minimum of 5+ years proven ...

Nvidia

Senior Package Layout Engineer - Hardware

OR · On-site +1

... in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA ... Electrical Engineering or equivalent experience * 5+ years experience in PCB Layout of graphics ...

Intel Corporation

Analog Engineer

Hillsboro, OR · On-site

$220K/yr

  • Medical

  • Retirement

  • PTO

... IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and ... Collaborate with architecture and layout teams to design circuits that maximize functionality ...

Intel

Analog Engineer

Hillsboro, OR

$220K/yr

  • Medical

  • Retirement

  • PTO

... IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and ... Collaborate with architecture and layout teams to design circuits that maximize functionality ...

Nvidia

OR · Hybrid

... in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA ... Electrical Engineering or equivalent experience * 5+ years experience in PCB Layout of graphics ...

Ralliant

Hardware Design Engineer

Beaverton, OR · On-site

Support PCB layout activities by working with senior engineers to define component placement ... Internship or project experience involving hardware or PCB design. * Experience with schematic ...

Actalent

PCB Design Engineer

Tualatin, OR · On-site

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Sr. PCB Design Engineer --- This Sr. PCB Design Engineer role focuses on end-to-end development of ... Establish layout standards and promote best practices within the PCB design team to improve ...

Andritz

Design Engineer

Eugene, OR · On-site

... layout drawings per instructions and concepts • Create multi-view detailed drawings, models, and ... engineering and design through fabrication and installation. We offer a collaborative work ...

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Internship Ic Layout Design Engineer information

What is the difference between Internship Ic Layout Design Engineer vs IC Design Engineer?

AspectInternship IC Layout Design EngineerIC Design Engineer
CredentialsTypically pursuing or recently completed relevant degree; internship experienceBachelor's or Master's in Electrical/Electronic Engineering; professional experience preferred
Work EnvironmentInternship programs, entry-level tasks, supervised environmentFull-time professional role, independent project work, team collaboration
ResponsibilitiesAssisting in layout design, learning design tools, supporting senior engineersDesigning, simulating, and verifying integrated circuit layouts independently

In summary, an Internship IC Layout Design Engineer is a trainee gaining hands-on experience under supervision, while an IC Design Engineer is a full-time professional responsible for designing and verifying integrated circuits independently.

What cities in Oregon are hiring for Internship Ic Layout Design Engineer jobs?

Cities in Oregon with the most Internship Ic Layout Design Engineer job openings:

Internship Ic Layout Design Engineer jobs near you

Analog Layout Design Engineer

Intel Corporation

Hillsboro, OR • On-site

$220K/yr

Full-time

Medical, Retirement, PTO

Re-posted 18 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:
Job Description:
The Role and Impact
Intel is seeking a passionate and skilled Analog Layout Design Engineer to join our diverse and inclusive team. As a critical contributor to our design ecosystem, you will drive the creation and optimization of complex layouts for analog signal circuits, ensuring that our designs meet stringent performance, area, and reliability requirements. Your work will directly impact Intel's cutting-edge technologies, enabling the development of innovative solutions that empower businesses and transform industries.
In this collaborative role, you will work with cross-functional teams, including analog circuit design, process technology, and package design, to deliver layouts that are efficient, robust, and aligned with our high standards of excellence. We welcome candidates from all backgrounds who are eager to contribute to groundbreaking advancements while expanding their expertise in layout methodologies.
What You'll Do
Key responsibilities will include but not limited to:
  • Design complex layouts of analog signal circuits based on detailed design specifications.
  • Conduct a comprehensive set of design verification checks, including process design rules, electron migration, voltage drop (IR), ESD, and other reliability assessments.
  • Develop and analyze floorplans, power grids, ESD structures, and bump layouts to meet performance and electrical requirements.
  • Perform floor planning and detailed signal planning for complex analog circuits, ensuring optimization for area, power, reliability, and performance.
  • Drive the development and implementation of innovative analog layout methodologies to improve productivity and layout quality.
  • Troubleshoot issues related to design, tools, flows, and methodologies utilized in analog layout design.
  • Collaborate closely with cross-disciplinary teams to meet design specifications, align on requirements, and negotiate layout tradeoffs.

Behavioral traits that we are looking for:
  • Collaboration: Works effectively in team environments and seeks input from others
  • Learning Agility: Demonstrates curiosity and quickly adapts to new tools, technologies, and concepts
  • Attention to Detail: Carefully reviews work to ensure accuracy and quality
  • Problem Solving: Approaches technical challenges with structured thinking and persistence
  • Accountability: Takes ownership of assigned tasks and follows through on deliverables
  • Communication: Clearly shares ideas and asks questions when clarification is needed
  • Growth Mindset: Open to feedback and continuously improving skills

Why Join Us
  • Work on cutting-edge semiconductor technologies
  • Learn from experienced engineers and mentors
  • Opportunities for career growth and technical development
  • Collaborative, inclusive engineering culture
  • Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
    • See Intel Benefits for more details.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel's immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field of study with 3+ years of experience. Or a Master's degree in the same field with 2+ years experience.
Your experience described above must be in the following:
  • Analog device and metal layout fundamentals, including analog/mixed-signal fundamentals
  • Cadence Virtuoso Layout Suite and Calibre/ ICV DRC for design and verification tasks
  • CMOS technologies and high-voltage rules
  • Floor planning and hierarchical layout planning for analog and mixed-signal blocks
  • Conducting performance verification for layouts and debug layout-related issues

Preferred Qualifications and Experience:
  • Strong understanding of analog layout effects including mismatch, parasitics, IR drop, electromigration (EM), and coupling, and their impact on circuit performance
  • Apply best practices for common-centroid, interdigitation, and symmetry-based layouts to minimize mismatch and variation
  • Evaluate and mitigate process variations and gradient effects across sensitive analog blocks
  • Ensure robust layout through parasitic-aware design, working closely with extraction (xtract/spef) and simulation teams
  • Debug layout-related issues by correlating LVS, DRC, xtract, and silicon behavior
  • Optimize layouts for noise isolation, shielding, and signal integrity, especially in mixed-signal environments

Join us in shaping the future of technology. Apply today and be part of a team that's driving innovation at Intel.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Texas, Austin
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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