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Ic Layout Design Engineer Jobs in Oregon (NOW HIRING)

Intel

Silicon Packaging Design Engineer

Hillsboro, OR

$148K/yr

Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and ... Engineering, or a STEM related field Experience listed above should be in the following:

Ralliant

Hardware Design Engineer

Beaverton, OR · On-site

Support PCB layout activities by working with senior engineers to define component placement, routing requirements, and design constraints. * Participate in board bring-up, debugging, and validation ...

Apple

Circuit Design Engineer - Library

Beaverton, OR · On-site

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

AllSTEM Connections

Layout Designer

Portland, OR · On-site

$74K - $118K/yr

Senior Facilities Layout & BIM Designer Role Overview We are seeking a Senior Facilities Layout ... the design intent. • Cross-Functional Liaison: Partner with engineering, facilities, and ...

ISAT Total Support

Design Engineer

Portland, OR · On-site

... layout on projects for all trades, configurations, and for the CBC, IBC, and UFC. * Product ... of engineering or design experience preferred (open to entry-level with strong aptitude)

Apple

Circuit Design Engineer - Library

Beaverton, OR

$142K - $263K/yr

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

Apple

Circuit Design Engineer - Library

Beaverton, OR

$142K - $263K/yr

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

Apple

Circuit Design Engineer - Library

Beaverton, OR

$142K - $263K/yr

Do you want to utilize your engineering background to make big things happen? Can you influence ... Design experience in advanced tech node device behavior with understanding of layout rules. Design ...

AST SpaceMobile

OR

$75K - $102K/yr

This role is responsible for structural architecture layout, primary and secondary structure design ... Bachelor's degree in mechanical engineering, aerospace engineering, or a related technical field ...

New

Noralogic Inc

Physical Design Engineer

Hillsboro, OR · On-site

$148K - $152K/yr

Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... of layout tasks, analysis of late changing process Additional Skills and or education: The ...

Noralogic Inc

Physical Design Engineer

Hillsboro, OR · On-site

$148K - $152K/yr

Physical Design Engineer Job Location: Hillsboro, OR Job Type: Fulltime In this position, you will ... of layout tasks, analysis of late changing process Additional Skills and or education: The ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

$210K/yr

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR

In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to ... IC development from definition to high-volume production including layout supervision, bench ...

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Showing results 21-40

All JobsIc Layout Design Engineer JobsIc Layout Design Engineer Jobs in Oregon

Ic Layout Design Engineer information

See Oregon salary details

$47.6K

$127.8K

$196.1K

How much do ic layout design engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for ic layout design engineer in Oregon is $127,771.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,200.00 and $152,200.00 per year, depending on experience, location, and employer.

What does an IC layout design engineer do?

An IC Layout Design Engineer is responsible for creating the physical design of integrated circuits (ICs) based on schematic designs. They ensure optimal placement and routing of transistors and interconnections while meeting performance, power, and area constraints. They work closely with circuit designers and verification engineers to ensure manufacturability and compliance with design rules. Tools like Cadence Virtuoso or Mentor Graphics are commonly used in this role.

What are the key skills and qualifications needed to thrive as an IC layout design engineer?

To thrive as an IC Layout Design Engineer, you need strong expertise in analog and/or digital IC layout, semiconductor device physics, and an educational background in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and proficiency with layout verification techniques (like DRC and LVS) are typically required. Exceptional attention to detail, effective communication, and the ability to collaborate closely with circuit design teams are valuable soft skills. These skills are essential to ensure the successful design, optimization, and integration of complex integrated circuits in high-performance environments.

What are the common challenges faced by IC layout design engineers on the job?

IC Layout Design Engineers often encounter challenges such as meeting strict design specification requirements, managing complex circuitry within limited silicon area, and ensuring layouts comply with manufacturing constraints. They may need to troubleshoot and resolve issues with DRC/LVS errors, work under tight project deadlines, and adapt quickly to changes in design parameters. Close collaboration with circuit design engineers and verification teams is common, requiring strong teamwork and effective communication. These challenges make the role dynamic and can provide excellent opportunities to develop specialized skills and advance into lead or principal engineering positions over time.

What are the most commonly searched types of Ic Layout Design Engineer jobs in Oregon? The most popular types of Ic Layout Design Engineer jobs in Oregon are:
What are popular job titles related to Ic Layout Design Engineer jobs in Oregon? For Ic Layout Design Engineer jobs in Oregon, the most frequently searched job titles are:
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Ic Layout Design Engineer jobs near you
Infographic showing various Ic Layout Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $127,771 per year, or $61.4 per hour.

Silicon Packaging Design Engineer

Intel

Hillsboro, OR

$148K/yr

Full-time

Medical, Retirement, PTO

Re-posted 10 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: 

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving the end-to-end development of silicon interposer and bridge designs that define the future of computing and connectivity. As a key contributor to Intel's cutting-edge technology, you will play a pivotal role in bridging silicon and hardware design, optimizing package performance, and delivering high-impact solutions that meet performance, cost, and manufacturability goals. Your expertise will directly contribute to Intel's mission to create world-changing technology that improves lives and connects communities worldwide.
Key Responsibilities:


- Design and implement physical layout and routing of silicon interposers and embedded bridges.
- Perform substrate fit and routing studies to evaluate design tradeoffs in performance, cost, and manufacturability.
- Collaborate closely with silicon, technology development and hardware teams to optimize system-level design, including silicon-package-board integration and pinout.
- Propose design updates changes for rules and conduct internal and external reviews to ensure design feasibility.
- Analyze design data and resolve design rule checks (DRCs) to achieve optimized and manufacturable package designs.
- Utilize industry-leading electronic design automation (EDA) tools, including Virtuoso, Innovus, FusionCompiler, ICvalidator, and Calibre, to create robust package layouts.
- Document processes and design specifications in the product lifecycle management system to ensure traceability and efficient collaboration.
- Conduct reviews with partner teams to close milestone requirements

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:


- Bachelor's degree with 3+ years of experience OR Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM related field

Experience listed above should be in the following:

  • Proficiency in custom layout and Auto-place-and-route EDA tools including Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or Calibre.
  • Experience with silicon physical layout design and development, routing interconnects, and/or review tools.

Additionally, the candidate should have at least one of the following:

  • 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals.
  • 1+ year of experience of Power Distribution and power integrity assessments.
  • 1+ year of experience of reliability requirements for interconnects.


Preferred Qualifications:

  • Familiarity with industry-leading silicon physical design methodologies and workflows.
  • Ability to effectively collaborate across multi-disciplinary teams and communicate technical concepts clearly.
  • A passion for innovation, problem-solving, and continuous improvement in a fast-paced environment.
  • Prior experience in optimizing silicon performance and conducting tradeoff studies for advanced packaging designs.

Join Intel and become an integral part of shaping tomorrow's technology today. Apply now to seize the opportunity to innovate, lead, and create meaningful impact on a global scale

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Benefits

Hours and flexibility

Workplace

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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