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Google Asic Design Engineer Jobs in Florida (NOW HIRING)

FPGA Design Engineer II

Miami, FL · On-site

$117K - $162K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Orlando, FL · On-site

$114K - $158K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

Working hand in hand with the Sales team, the Design Engineer designs and quotes certified ... Microsoft Edge, Google Chrome and Mozilla Firefox * Adobe Acrobat X Professional * Windows 10 ...

Working hand in hand with the Sales team, the Design Engineer designs and quotes certified ... Microsoft Edge, Google Chrome and Mozilla Firefox * Adobe Acrobat X Professional * Windows 10 ...

Senior FPGA Design Engineer

Orlando, FL · On-site

$114K - $158K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... Experience with integration and debug of FPGA/ASIC devices * Radar processing techniques * Image ...

Senior FPGA Design Engineer

Miami, FL · On-site

$117K - $162K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... Experience with integration and debug of FPGA/ASIC devices * Radar processing techniques * Image ...

Mechanical Design Engineer III

Orlando, FL · On-site

$70K - $96K/yr

... Google, Beyoncé, and The Olympics Position Purpose: Mechanical Design Engineers (MDE) at TAIT are responsible for project-based mechanical design work that focuses on specialized machinery ...

Mechanical Design Engineer III

Orlando, FL · On-site

$70K - $96K/yr

... Google, Beyoncé, and The Olympics Position Purpose: Mechanical Design Engineers (MDE) at TAIT are responsible for project-based mechanical design work that focuses on specialized machinery ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 5+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 7+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 7+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 5+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 7+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 5+ years of experience or ...

Sr. RTL Engineer

Orlando, FL · On-site

$100 - $130/hr

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience * BS in Electrical Engineering or related field and 5+ years of experience or ...

FPGA Engineer II (ONSITE)

Melbourne, FL · On-site

$114K - $157K/yr

Collins Aerospace is seeking a FPGA Engineer II for the CNS (Communication, Navigation ... ASIC/FPGA/MPSoC digital architecture development and design. * Develop RTL design code and ...

Showing results 21-40

Google Asic Design Engineer information

See Florida salary details

$70.2K

$112.2K

$151K

How much do google asic design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for google asic design engineer in Florida is $112,240.00, according to ZipRecruiter salary data. Most workers in this role earn between $98,300.00 and $134,500.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What job categories do people searching Google Asic Design Engineer jobs in Florida look for?

The top searched job categories for Google Asic Design Engineer jobs in Florida are:

What cities in Florida are hiring for Google Asic Design Engineer jobs?

Cities in Florida with the most Google Asic Design Engineer job openings:

Infographic showing various Google Asic Design Engineer job openings in Florida as of August 2026, with employment types broken down into 5% As Needed, 77% Full Time, and 18% Contract. Highlights an 95% In-person, and 5% Remote job distribution, with an average salary of $112,240 per year, or $54 per hour.

Senior Principal Electrical Engineer-FPGA Design - Onsite Tucson, AZ

Raytheon

Orlando, FL

$97K - $130K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 6 days ago


RTX rating

8.2

Company rating: 8.2 out of 10

Based on 86 frontline employees who took The Breakroom Quiz

38th of 72 rated aerospace companies


Job description

Date Posted:

2026-07-31

Country:

United States of America

Location:

US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02

Position Role Type:

Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements:

Active and transferable U.S. government issued security clearance is required prior to start date.​ U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance​

Security Clearance Type:

DoD Clearance: Secret

Security Clearance Status:

Ability to obtain INTERIM U.S. government issued security clearance is required prior to start date

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world. 

The Effector Digital Products (EDP) department develops electronics for our weapon system products. We are responsible for the architecture, design, and documentation of deliverable FPGA embedded processing. We engage at the outset of the weapon system development and follow our designs through deployment. Our products are deployed all over the world, from the ground to exoatmospheric environments and into space. 

As a Senior Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces.

Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.

This position is 100% ONSITE in Tucson, Arizona.

What You Will Do

  • Leader of FPGA-based systems architecture, and design to include determination of parts, interfaces, and Concept of Operations (CONOPS).  Delivering quality releases from initial proof of concept up through production.

  • Establish processes and operational plans for a project.

  • Independently drive projects and execute to program schedules on time and budget.

  • May lead large integrated or cross product teams on moderate to large multi-year programs.

  • Design, develop, implement and verify highly complex configurable logic solutions for products that significantly improves on an existing product.

  • Solve problems that are numerous and typically undefined where information is difficult to obtain.

  • Conducts extensive investigation to understand root cause of problems. 

  • Communicates with parties within and outside of own function which would include customers, vendors, and executive leadership. 

  • Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)

  • Translate system-level requirements into FPGA requirements.

  • Design and code in VHDL for reliability and maintainability.

  • Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage.

  • Create complete documentation including requirements, verification plans, and user’s guides.

  • Viewed as subject-matter expert within discipline

  • Coaches, reviews, and delegates work to junior engineers

  • Support internal and external technical reviews

  • Support customer interactions and relations

  • Make improvements to processes, systems or products to enhance overall performance

Qualifications You Must Have

  • Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 10 years of prior relevant experience

  • System level FPGA requirements specification and architecture development and the ability to identify links and potential impact on projects, programs or systems. 

  • Proposal experience to include basis of estimate generation, resource identification, and constraint -based program schedule planning.

  • Strong understanding of design hand-off requirements for system requirements, configurable logic, software, mechanical analysis and tests. 

  • FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

  • Xilinx or Microsemi devices and flow tools

Qualifications We Prefer

  • ​FPGA design experience in one or more of the following areas:

  • Radar processing techniques

  • Image processing techniques for visual and infrared sensors

  • Embedded systems design using ARM, Microblaze, or Nios processors

  • Gigabit serial interfaces and multi-gigabit transceivers (MGT’s)

  • Understanding of assertion-based verification and UVM using System Verilog 

  • Verification utilizing emulation platforms 

  • Experience leading technical teams and programs

  • Revision control and documentation release processes 

  • Deep knowledge of project management

What We Offer

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Safety, Trust, Respect, Accountability, Collaboration, and Innovation.

  • This position offers relocation

Learn More & Apply Now!

Please consider the following role type definition as you apply for this role:

Employees who are working in Onsite roles will work primarily onsite. This includes all production and maintenance employees, as they are essential to the development of our products.

This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website here: https://www.state.gov/m/ds/clearances/c10978.htm

This position is in beautiful Tucson, AZ. Tucson has a friendly, caring and laid-back atmosphere, combined with the innovation and energy of a metropolitan region and recognized as one of America’s 10 Best Small Cities. Surrounded by beautiful mountains, colorful Sonoran Desert landscape and majestic saguaro cacti, Tucson is blessed with some of nature’s best work. Tucson is known for its bright blue skies, and with more than 310 sunny days per year, Tucson’s fantastic weather lets residents enjoy the outdoors year-round.

Tucson, AZ: https://careers.rtx.com/global/en/raytheon-tucson,-az-location

#LI-CV1

As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.

The salary range for this role is 132,400 USD - 251,600 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills. Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement. Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance. This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply. RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.

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About RTX

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing, it services, aerospace product and parts manufacturing and engineering professional services

Company size

10,000+ Employees

Headquarters location

Waltham, MA, US

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