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Google Asic Design Engineer Jobs in Florida (NOW HIRING)

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 5+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 7+ years of experience or ...

Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education and Experience: * BS in Electrical Engineering or related field and 5+ years of experience or ...

Mechanical Design Engineer III-Theme Park

Orlando, FL · On-site

$70K - $96K/yr

... Google, Beyoncé, and The Olympics Position Purpose: Mechanical Design Engineers (MDE) at TAIT are responsible for project-based mechanical design work that focuses on specialized machinery ...

... Google, Beyoncé, and The Olympics Position Purpose: Mechanical Design Engineers (MDE) at TAIT are responsible for project-based mechanical design work that focuses on specialized machinery ...

Google Cloud Engineer

Tampa, FL · Remote

$52.75 - $70.50/hr

Experience developing technical architecture documents, driving design decisions, developing ... programming languages (e.g. Python) * Strong understanding of Google Cloud services and ...

CCaaS Google Data Engineer

Sunrise, FL · On-site

$109K - $131K/yr

Design and implement scalable CCaaS and IVA solutions, including conversational IVR design, NLU/NLP modeling, intent and flow orchestration, webhook integrations, and speech-to-text/text-to-speech.

FPGA Engineer

Melbourne, FL · On-site

$120K - $154K/yr

Experience with design on Xilinx products would be a strong plus * expected to communicate ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...

Showing results 21-40

Google Asic Design Engineer information

See Florida salary details

$70.2K

$112.2K

$151K

How much do google asic design engineer jobs pay per year?

As of Aug 13, 2026, the average yearly pay for google asic design engineer in Florida is $112,240.00, according to ZipRecruiter salary data. Most workers in this role earn between $98,300.00 and $134,500.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What cities in Florida are hiring for Google Asic Design Engineer jobs?

Cities in Florida with the most Google Asic Design Engineer job openings:

Infographic showing various Google Asic Design Engineer job openings in Florida as of August 2026, with employment types broken down into 5% As Needed, 76% Full Time, and 19% Contract. Highlights an 95% In-person, and 5% Remote job distribution, with an average salary of $112,240 per year, or $54 per hour.

Sr. RTL Engineer

MicroVision

Orlando, FL • On-site

Full-time

Medical, Dental, Vision, Life, Retirement

Re-posted 5 days ago


Job description

About us: 

With offices in the U.S. and Germany, MicroVision is at the forefront of driving the global adoption of innovative perception solutions, with the goal of making mobility and autonomy safer. Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg, Germany, enables us to develop and supply integrated lidar hardware and perception software solutions. Our proprietary technologies enhance safety and automation across various industrial applications, including robotics, automated warehouses, and agriculture, and are instrumental in the development of autonomous systems. MicroVision's core technology, initially developed for the automotive industry, continues to accelerate advanced driver-assistance systems (ADAS) and autonomous driving. Building on our history of providing technology to the military segment, our target offerings include semi- and fully autonomous airborne and terrestrial sensor systems. With our solid-state lidar technologies, encompassing MEMS-based long-range lidar and flash-based short-range lidar, integrated with our onboard perception software, MicroVision possesses the expertise to deliver safe mobility at the speed of life.   

Job Summary:  

MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of MicroVision's growing Digital Design Engineering team, you will collaborate with various technical teams in the company to design and take into production, market defining Automotive LiDAR product. The right candidate for this position will be a highly motivated FPGA/RTL Engineer with a breadth of understanding in FPGA design and best practices, including detailed design, System Verilog coding, modelling, simulation, verification, integration and test. 

Essential Duties and Responsibilities:  

  • Derive FPGA requirements based on system requirements then create FPGA architecture to fulfill those requirements 

  • Design, implement and test Register-Transfer Level (RTL) features and components guided by system architecture and requirements 

  • Own the detailed design of assigned firmware components and subsystem functionality 

  • Document test and implementation plans at unit at system levels and then execute on it. 

  • Work with other teams to integrate developed features into system hardware. 

  • Support bringing up RTL features developed by the team. 

  • Coach/mentor junior members of RTL and integration teams to complete tasks. 

  • Participate in the full software development life cycle (SDLC) flow including peer reviews of requirements, architecture, design, and code implementations within an approved ASPICE development flow. 

Required Knowledge, Skills and Abilities:  

  • Knowledge of System Verilog, Verilog, Python programming languages 

  • Proficient in FPGA Design methodologies from state machine design to DSP implementation 

  • Experienced in closing timing in FPGA designs. 

  • Mapping algorithms to FPGA appropriate logic implementations 

  • Expert integrating and bringing up features in hardware. 

  • Ability to work well in a fast-moving and complex environment. 

  • Independently driven to complete project tasks 

  • Experience with Configuration Management and Change Control concepts and tools (Git, Subversion, Jira, etc.) 

  • Experience working with Functional Requirements and defining Requirement Based Tests 

  • Experience performing HDL Synthesis/Simulation (eg. VCS, Synplicity, etc.) 

  • Experience with design analyses (Timing, Lint, Clock Domain Crossings, Code Coverage, etc.) and IP compliance strategies 

  • Experience designing portable, scalable Test Benches 

  • Experience with UVM/OVM - Constrained random testing 

  • Familiarity with hierarchical simulation and verification frameworks 

  • Experience with intersystem communication protocols (I2C, UART, SPI, etc.) 

  • Familiarity with microcontroller peripherals including one or more of the following: ADCs, DACs, Flash, EEPROM, timers and watchdogs 

  • Working knowledge of data structures and algorithm fundamentals 

  • Working knowledge of digital and analog electronics 

Preferred Knowledge, Skills, and Abilities 

  • Knowledgeable of control systems and digital signal processing fundamentals 

  • Proficient in other embedded software systems developed in C / Cpp / etc. 

  • Hands on experience with High-Level Synthesis (HLS) 

  • Excellent scripting and automation skills. Bash shell, python, Make/CMake, and TCL desired 

  • Extensive project experience working on embedded laser applications including Lidar 

  • Safety-critical industry experience. (FIT analysis, etc.) 

  • Working knowledge of various computing architectures beyond FPGAs, such as DSPs, GPUs, or MCUs, and their associated hardware computing platforms used to program them 

  • Experience with ASIC design & migration from FPGA prototypes to production ASICs 

Required Education and Experience: 

  • BS in Electrical Engineering or related field and 5+ years of experience or equivalent combination of education and experience 

 MicroVision offers flexible work schedule that could include a hybrid schedule of onsite and remote work subject to team and business needs. You must live and reside within commuting distance from MicroVision's office in Orlando, FL. 

We are not able to provide visa sponsorship for this position. You must be able to work in the US without sponsorship. 

Benefits: 

MicroVision is also proud to offer a comprehensive benefit program including: 

  • Competitive compensation and equity program 

  • Choice between an HSA Medical plan or a Buy-Up PPO Medical plan 

  • Dental plan 100% employer-paid for employees  

  • Vision coverageVision coverage 100% employer-paid for employees 

  • 401k plan with company match to help you save for your future (50% of your contributions up to the first 6% of your eligible pay) 

  • Generous time off package including a flexible vacation program as well as incidental personal/sick days and floating holidays 

  • Supplemental pay for Parental Leave 

  • Company-paid basic life and AD&D insurance and long-term disability. 

 

MicroVision is committed to an inclusive workplace. MicroVision is an equal opportunity employer and does not discriminate on the basis of race, creed, color, religion, national origin, sex, age, disability, marital status, sexual orientation, status as a disabled veteran or Vietnam-era veteran or any other basis prohibited by local, state or federal law.Please let us know if you need reasonable accommodation in completing the application, attending and/or participating in an interview or in taking any test required for employment. 

MicroVision is an E-Verify participant. We will provide the Social Security Administration, and if necessary, the Department of Homeland Security, with information from each new employees' Form I-9 to confirm work authorization. Please note that we do not use this information to pre-screen job applicants. 

Visit our website at www.microvision.com to learn more about our company. 

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