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Full Time Physical Verification Engineer Jobs (NOW HIRING)

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$184K - $324K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$184K - $324K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$150K - $277K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Intel Corporation

CPU Verification Engineer

Austin, TX · On-site

$134K/yr

The Role and Impact As a CPU Design Verification Engineer , you'll play a pivotal role in ensuring ... Working alongside world-class CPU architects, RTL designers, and physical design teams, you'll help ...

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Full Time Physical Verification Engineer information

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$80K

$142.6K

$203.5K

How much do full time physical verification engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for full time physical verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a full time physical verification engineer do?

A Full Time Physical Verification Engineer is responsible for ensuring that integrated circuit (IC) designs meet all manufacturing requirements before production. Their main tasks include running design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC) to verify that the physical layout matches the intended circuit and adheres to foundry specifications. They work closely with design, layout, and fabrication teams to identify and resolve any issues that could affect chip functionality or yield. Attention to detail and proficiency with electronic design automation (EDA) tools are essential for this role.

What are the key skills and qualifications needed to thrive as a full time physical verification engineer, and why are they important?

To thrive as a Full Time Physical Verification Engineer, you need expertise in VLSI design, semiconductor physics, and a degree in electrical or electronics engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, along with knowledge of DRC, LVS, and parasitic extraction checks, is essential. Strong problem-solving skills, attention to detail, and effective communication help engineers collaborate with design teams and resolve complex verification issues. These skills ensure the accuracy and manufacturability of integrated circuit designs, which is critical for successful chip production.

What are some common challenges faced by full time physical verification engineers, and how can they be addressed?

Full Time Physical Verification Engineers often encounter challenges such as managing tight project deadlines, debugging complex design rule violations, and ensuring seamless communication with design and layout teams. Staying updated with the latest verification tools and methodologies is essential to efficiently identify and resolve errors. Proactive collaboration and regular cross-team meetings can help address misunderstandings early, while leveraging automation scripts can reduce repetitive tasks and improve accuracy. Continuous learning and seeking feedback from peers are effective strategies to overcome these challenges.

What is the difference between Full Time Physical Verification Engineer vs Physical Design Engineer?

AspectFull Time Physical Verification EngineerPhysical Design Engineer
Primary RoleVerifies physical layouts for manufacturability and design rule complianceCreates and optimizes physical layouts for chip design
Skills & CertificationsKnowledge of DRC, LVS, parasitic extraction; familiarity with EDA toolsExperience with placement, routing, and physical implementation tools
Work EnvironmentDesign verification teams in semiconductor or chip design companiesPhysical implementation teams in IC design firms

While both roles focus on physical aspects of chip design, the Full Time Physical Verification Engineer primarily verifies layouts for correctness, whereas the Physical Design Engineer focuses on creating and optimizing the physical layout. Both roles require similar technical skills and often collaborate closely during the chip development process.

More about Full Time Physical Verification Engineer jobs

What are the most commonly searched types of Physical Verification Engineer jobs?

The most popular types of Physical Verification Engineer jobs are:

What states have the most Full Time Physical Verification Engineer jobs?

States with the most job openings for Full Time Physical Verification Engineer jobs include:

What are popular job titles related to Full Time Physical Verification Engineer jobs?

For Full Time Physical Verification Engineer jobs, the most frequently searched job titles are:

Full Time Physical Verification Engineer jobs near you
Infographic showing various Full Time Physical Verification Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 74% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Senior Physical Verification CAD Engineer

Mountain View, CA • On-site

Microsoft
Computer and Computer Peripheral Equipment and Software Wholesalers • 10K+ employees
Learn more about Microsoftexternal

$160K - $165K/yr

Full-time

Re-posted 17 days ago

Microsoft rating

8.6

Company rating: 8.6 out of 10

Based on 134 frontline employees who took The Breakroom Quiz

Job description

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
Do you have a passion for advanced silicon signoff and physical verification at leading-edge technology nodes? You will be part of a team responsible for driving state-of-the-art Physical Verification CAD solutions for Microsoft's silicon design teams. In this role, you will foster the enablement and support of advanced-node DRC, LVS, Antenna, and ESD signoff flows, working closely with EDA vendors, and internal design teams. You will own PV signoff methodology end to end, identify gaps, and drive scalable, production-ready solutions across multiple silicon programs. We are committed to a diverse and inclusive workspace and strongly encourage applicants from all backgrounds and walks of life. Difference makes us better.
We are looking for a Senior Physical Verification CAD Engineer to join our team.
Responsibilities
  • Develop, maintain, and support Physical Verification (PV) flows across all Silicon projects, spanning early design (shift-left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks

  • Work on PV-related flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross-tool debug.

  • Participate in cross functional alignment with CAD, Technology, and external EDA partners to communicate PV requirements, influence roadmap priorities, and unblock execution at critical project milestones.

  • Support PDK and node enablement activities, ensuring PV flows are validated, production ready, and aligned with foundry decks and internal signoff criteria across multiple technology variants.

  • Contribute to PV activities, including training material, documentation, onboarding labs, and continuous improvement of automation and debug infrastructure.

  • Development and deployment of AI-enabled agents to automate and optimize Physical Verification (PV) and PERC workflows across the Silicon organization.

Qualifications
Minimum Qualifications:
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
    • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
    • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
    • OR equivalent experience.

Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:
  • BS + 7 years / MS + 5 years of relevant experience in Physical Verification, Physical Design, or CAD methodology roles.

  • Strong hands-on experience with Physical Verification checks, including: Base and Metal DRC, LVS, ERC, Antenna, etc.

  • Proficiency with industry standard PV tools, such as Calibre.

  • Solid scripting skills in at least one language (TCL, Python, Perl, or equivalent) for flow automation, debug, and data analysis.

  • Ability to debug complex, cross domain issues, reason about root cause (design vs flow vs tool), and drive issues to closure across teams.

  • SVRF rule or deck enablement experience, including customization, and debug support.

  • Experience with advanced verification checks, such as: PERC (including custom or CNOD based checks), ESD, EOS, level shifter, and reliability focused verification.

  • Exposure to shift left PV methodologies, TCIC flows, and early-stage verification strategies that improve convergence and reduce late-stage surprises.

  • Prior experience contributing to or leading PV, methodology councils, or multi project enablement efforts.

#SCHIE #azurehwjobs
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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