ZipRecruiter

Log In

2

Full Time Physical Verification Engineer Jobs (NOW HIRING)

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC ...

Apple

SoC Physical Design Verification Engineer

Austin, TX · On-site

$134K - $138K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC ...

Apple

SoC Physical Design Verification Engineer

Beaverton, OR · On-site

$141K - $145K/yr

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ...

Apple

SoC Physical Design Verification Engineer

Austin, TX

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

Apple

SoC Physical Design Verification Engineer

Austin, TX

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

... engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. Preferred Qualifications Experienced with physical verification flows such as ...

previous pagenext page

Showing results 21-40

All Jobsfull time JobsTechnology JobsSoftware JobsSoftware Quality Engineer JobsFull Time Physical Verification Engineer Jobs

Full Time Physical Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do full time physical verification engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for full time physical verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What does a full time physical verification engineer do?

A Full Time Physical Verification Engineer is responsible for ensuring that integrated circuit (IC) designs meet all manufacturing requirements before production. Their main tasks include running design rule checks (DRC), layout versus schematic (LVS) checks, and electrical rule checks (ERC) to verify that the physical layout matches the intended circuit and adheres to foundry specifications. They work closely with design, layout, and fabrication teams to identify and resolve any issues that could affect chip functionality or yield. Attention to detail and proficiency with electronic design automation (EDA) tools are essential for this role.

What are the key skills and qualifications needed to thrive as a full time physical verification engineer, and why are they important?

To thrive as a Full Time Physical Verification Engineer, you need expertise in VLSI design, semiconductor physics, and a degree in electrical or electronics engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, along with knowledge of DRC, LVS, and parasitic extraction checks, is essential. Strong problem-solving skills, attention to detail, and effective communication help engineers collaborate with design teams and resolve complex verification issues. These skills ensure the accuracy and manufacturability of integrated circuit designs, which is critical for successful chip production.

What are some common challenges faced by full time physical verification engineers, and how can they be addressed?

Full Time Physical Verification Engineers often encounter challenges such as managing tight project deadlines, debugging complex design rule violations, and ensuring seamless communication with design and layout teams. Staying updated with the latest verification tools and methodologies is essential to efficiently identify and resolve errors. Proactive collaboration and regular cross-team meetings can help address misunderstandings early, while leveraging automation scripts can reduce repetitive tasks and improve accuracy. Continuous learning and seeking feedback from peers are effective strategies to overcome these challenges.

What is the difference between Full Time Physical Verification Engineer vs Physical Design Engineer?

AspectFull Time Physical Verification EngineerPhysical Design Engineer
Primary RoleVerifies physical layouts for manufacturability and design rule complianceCreates and optimizes physical layouts for chip design
Skills & CertificationsKnowledge of DRC, LVS, parasitic extraction; familiarity with EDA toolsExperience with placement, routing, and physical implementation tools
Work EnvironmentDesign verification teams in semiconductor or chip design companiesPhysical implementation teams in IC design firms

While both roles focus on physical aspects of chip design, the Full Time Physical Verification Engineer primarily verifies layouts for correctness, whereas the Physical Design Engineer focuses on creating and optimizing the physical layout. Both roles require similar technical skills and often collaborate closely during the chip development process.

More about Full Time Physical Verification Engineer jobs

What are the most commonly searched types of Physical Verification Engineer jobs?

The most popular types of Physical Verification Engineer jobs are:

What states have the most Full Time Physical Verification Engineer jobs?

States with the most job openings for Full Time Physical Verification Engineer jobs include:

What job categories do people searching Full Time Physical Verification Engineer jobs look for?

The top searched job categories for Full Time Physical Verification Engineer jobs are:

Full Time Physical Verification Engineer jobs near you
Infographic showing various Full Time Physical Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 18% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

PD - Sr Staff - Physical Verification Lead \u007C Signoff & DRC

Eliyan

Mundelein, IL • On-site

Full-time

Re-posted 10 days ago

Job description

ABOUT THE ROLE

As a Sr Staff / Principal Physical Verification Engineer, you will be the technical owner of all signoff physical verification activities across advanced process nodes. You will lead DRC, LVS, and DFM sign-off at chip top level, drive hierarchical verification strategies, and own bump planning and package-level DRC across Intel, TSMC, Samsung, and GlobalFoundries technologies spanning 28nm through 2nm. You will be a partner with physical design, package engineering, and foundry teams to ensure first-pass tape out success on chiplet-based products.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.